Henry Cook 81e136aa37 rocket: give l2 tlb a nice name

2017-09-21 18:13:39 -07:00

..

ALU.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

AMOALU.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Breakpoint.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

BTB.scala

Fix BTB not being refilled on some indirect jumps

2017-07-26 02:13:43 -07:00

BusErrorUnit.scala

Report TL errors into D$

2017-09-20 00:05:07 -07:00

Consts.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

CSR.scala

Rename trace.addr -> iaddr

2017-09-20 14:32:41 -07:00

DCache.scala

Revert "try to give seqmems clearer names"

2017-09-21 18:02:32 -07:00

Decode.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Events.scala

Add method to print perf events

2017-07-25 15:19:16 -07:00

Frontend.scala

Report I$ errors

2017-09-20 00:05:07 -07:00

HellaCache.scala

Report D$ errors

2017-09-20 00:05:07 -07:00

HellaCacheArbiter.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

IBuf.scala

Add instruction-trace port

2017-09-19 22:59:57 -07:00

ICache.scala

Revert "try to give seqmems clearer names"

2017-09-21 18:02:32 -07:00

IDecode.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Instructions.scala

Add RVC instruction patterns

2017-07-25 15:19:16 -07:00

Multiplier.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

NBDcache.scala

Revert "try to give seqmems clearer names"

2017-09-21 18:02:32 -07:00

package.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

PMP.scala

Use UIntToOH1 (#921)

2017-08-03 14:55:39 -07:00

PTW.scala

rocket: give l2 tlb a nice name

2017-09-21 18:13:39 -07:00

RocketCore.scala

Rename trace.addr -> iaddr

2017-09-20 14:32:41 -07:00

RVC.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

ScratchpadSlavePort.scala

Add an intra-tile xbar

2017-09-20 00:05:07 -07:00

SimpleHellaCacheIF.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

TLB.scala

config: use Field defaults over Config defaults

2017-09-13 11:25:42 -07:00

TLBPermissions.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00