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ALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AMOALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Breakpoint.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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BTB.scala
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Fix BTB not being refilled on some indirect jumps
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2017-07-26 02:13:43 -07:00 |
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BusErrorUnit.scala
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Report TL errors into D$
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2017-09-20 00:05:07 -07:00 |
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Consts.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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CSR.scala
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Rename trace.addr -> iaddr
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2017-09-20 14:32:41 -07:00 |
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DCache.scala
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Revert "try to give seqmems clearer names"
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2017-09-21 18:02:32 -07:00 |
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Decode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Events.scala
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Add method to print perf events
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2017-07-25 15:19:16 -07:00 |
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Frontend.scala
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Report I$ errors
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2017-09-20 00:05:07 -07:00 |
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HellaCache.scala
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Report D$ errors
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2017-09-20 00:05:07 -07:00 |
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HellaCacheArbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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IBuf.scala
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Add instruction-trace port
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2017-09-19 22:59:57 -07:00 |
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ICache.scala
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Revert "try to give seqmems clearer names"
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2017-09-21 18:02:32 -07:00 |
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IDecode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Instructions.scala
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Add RVC instruction patterns
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2017-07-25 15:19:16 -07:00 |
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Multiplier.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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NBDcache.scala
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Revert "try to give seqmems clearer names"
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2017-09-21 18:02:32 -07:00 |
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package.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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PMP.scala
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Use UIntToOH1 (#921)
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2017-08-03 14:55:39 -07:00 |
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PTW.scala
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rocket: give l2 tlb a nice name
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2017-09-21 18:13:39 -07:00 |
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RocketCore.scala
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Rename trace.addr -> iaddr
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2017-09-20 14:32:41 -07:00 |
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RVC.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ScratchpadSlavePort.scala
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Add an intra-tile xbar
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2017-09-20 00:05:07 -07:00 |
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SimpleHellaCacheIF.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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TLB.scala
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config: use Field defaults over Config defaults
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2017-09-13 11:25:42 -07:00 |
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TLBPermissions.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
