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riscv/rocket-chip
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45d26ea1304968683a07317088c96fff42b2404e
rocket-chip/src/main/scala/coreplex
T
History
Henry Cook 9d5e96672e coreplex: clean up coherence manager attachment point
2017-09-25 18:07:51 -07:00
..
BaseCoreplex.scala
tile: remove PAddrBits in favor of SharedMemoryTLEdge
2017-09-08 13:53:36 -07:00
Configs.scala
coreplex: clean up coherence manager attachment point
2017-09-25 18:07:51 -07:00
FrontBus.scala
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
InterruptBus.scala
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
MemoryBus.scala
coreplex: clean up coherence manager attachment point
2017-09-25 18:07:51 -07:00
PeripheryBus.scala
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
Ports.scala
ports: use BigInts instead of Longs and the new x"..." context
2017-09-13 11:25:42 -07:00
ResetVector.scala
tile: remove global Field ResetVectorBits
2017-09-08 14:50:59 -07:00
RocketCoreplex.scala
Integrate L1 BusErrorUnit
2017-09-20 00:05:07 -07:00
RTC.scala
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
SystemBus.scala
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
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