926efd0cab
We're building a chip with 8 memory channels. Since this will require a complicated test setup we want to also be able to bring up the chip with fewer memory channels. This commit adds a SCR that controls the number of active memory channels on a chip. Toggling this SCR will scramble memory and drop Nasti messages, so it's only possible to change while the chip is booting. By default this just adds a 1-bit SCR, which essentially no extra logic. When multiple memory channel configurations are enabled at elaboration time, a NastiMemoryInterconnect is generated for each channel configuration. The number of outstanding misses is increased to coorespond to the maximum number of banks per memory channel (added as a parameter), which I believe is necessary to avoid deadlock in the memory system. A configuration is added that supports 8 memory channels but has only 1 enabled by default.
47 lines
1.0 KiB
C++
47 lines
1.0 KiB
C++
// See LICENSE for license details.
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#ifndef _HTIF_EMULATOR_H
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#define _HTIF_EMULATOR_H
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#include <fesvr/htif_pthread.h>
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class htif_emulator_t : public htif_pthread_t
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{
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int memory_channel_mux_select;
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public:
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htif_emulator_t(uint32_t memsz_mb, const std::vector<std::string>& args)
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: htif_pthread_t(args),
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memory_channel_mux_select(0)
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{
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this->_memsz_mb = memsz_mb;
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for (const auto& arg: args) {
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if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27))
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memory_channel_mux_select = atoi(arg.c_str()+27);
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}
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}
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void set_clock_divisor(int divisor, int hold_cycles)
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{
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write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16);
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}
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void start()
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{
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set_clock_divisor(5, 2);
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write_cr(-1, UNCORE_SCR__MEMORY_CHANNEL_MUX_SELECT, memory_channel_mux_select);
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htif_pthread_t::start();
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}
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uint32_t mem_mb() {
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uint32_t scr_mb = htif_pthread_t::mem_mb();
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return (_memsz_mb < scr_mb) ? _memsz_mb : scr_mb;
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}
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private:
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uint32_t _memsz_mb;
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};
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#endif
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