56 lines
1.3 KiB
Scala
56 lines
1.3 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import RocketChipBackend._
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import scala.collection.mutable.HashMap
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object RocketChipBackend {
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val initMap = new HashMap[Module, Bool]()
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}
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class RocketChipBackend extends VerilogBackend
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{
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initMap.clear()
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override def emitPortDef(m: MemAccess, idx: Int) = {
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val res = new StringBuilder()
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for (node <- m.mem.inputs) {
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if(node.name.contains("init"))
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res.append(" .init(" + node.name + "),\n")
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}
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(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
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}
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def addMemPin(c: Module) = {
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for (m <- Driver.components) {
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m bfs { _ match {
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case mem: Mem[_] if mem.seqRead =>
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connectMemPin(m, mem)
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case _ =>
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} }
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}
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}
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def connectInitPin(c: Module) {
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initMap(c) = c.addPin(Bool(INPUT), "init")
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if (!(initMap contains c.parent)) connectInitPin(c.parent)
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initMap(c) := initMap(c.parent)
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}
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def connectMemPin(c: Module, mem: Mem[_]) {
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if (!(initMap contains c)) connectInitPin(c)
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mem.inputs += initMap(c)
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}
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def addTopLevelPin(c: Module) = {
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initMap(c) = c.addPin(Bool(INPUT), "init")
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}
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transforms += addTopLevelPin
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transforms += addMemPin
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}
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class Fame1RocketChipBackend extends RocketChipBackend with Fame1Transform
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