303 lines
10 KiB
Scala
303 lines
10 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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class BaseCoreplexConfig extends Config ((site, here, up) => {
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// Tile parameters
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case XLen => 64 // Applies to all cores
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case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
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case BuildCore => (p: Parameters) => new Rocket()(p)
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// Interconnect parameters
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case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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// Additional device Parameters
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case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
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case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
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case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
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})
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/* Composable partial function Configs to set individual parameters */
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class WithNBigCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => {
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val big = RocketTileParams(
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core = RocketCoreParams(mulDiv = Some(MulDivParams(
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mulUnroll = 8,
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mulEarlyOut = true,
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divEarlyOut = true))),
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusKey).beatBits,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusKey).beatBits,
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blockBytes = site(CacheBlockBytes))))
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List.tabulate(n)(i => big.copy(hartid = i))
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}
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})
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class WithNSmallCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => {
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val small = RocketTileParams(
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core = RocketCoreParams(useVM = false, fpu = None),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusKey).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusKey).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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blockBytes = site(CacheBlockBytes))))
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List.tabulate(n)(i => small.copy(hartid = i))
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}
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})
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class With1TinyCore extends Config((site, here, up) => {
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case XLen => 32
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case RocketTilesKey => List(RocketTileParams(
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core = RocketCoreParams(
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useVM = false,
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fpu = None,
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mulDiv = Some(MulDivParams(mulUnroll = 8))),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusKey).beatBits,
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nSets = 256, // 16Kb scratchpad
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nWays = 1,
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nTLBEntries = 4,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes),
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scratch = Some(0x80000000L))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusKey).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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blockBytes = site(CacheBlockBytes)))))
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case RocketCrossingKey => List(RocketCrossingParams(
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crossingType = SynchronousCrossing(),
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master = TileMasterPortParams(cork = Some(true))
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))
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})
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class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
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case BankedL2Key => up(BankedL2Key, site).copy(nBanksPerChannel = n)
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})
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class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
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case BroadcastKey => up(BroadcastKey, site).copy(nTrackers = n)
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})
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// This is the number of icache sets for all Rocket tiles
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class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(icache = r.icache.map(_.copy(nSets = sets))) }
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})
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// This is the number of icache sets for all Rocket tiles
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class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nSets = sets))) }
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})
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class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(icache = r.icache.map(_.copy(nWays = ways)))
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}
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})
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class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nWays = ways)))
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}
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})
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class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
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case CacheBlockBytes => linesize
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})
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class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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case BroadcastKey => up(BroadcastKey, site).copy(bufferless = true)
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})
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/**
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* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
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*
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* There is a very restrictive set of conditions under which the stateless
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* bridge will function properly. There can only be a single tile. This tile
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* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
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* uncached channel capable of writes (i.e. a RoCC accelerator).
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*
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* This is because the stateless bridge CANNOT generate probes, so if your
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* system depends on coherence between channels in any way,
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config((site, here, up) => {
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case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
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implicit val p = coreplex.p
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val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
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(ww.node, ww.node, () => None)
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})
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})
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class WithRV32 extends Config((site, here, up) => {
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case XLen => 32
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(
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mulDiv = Some(MulDivParams(mulUnroll = 8)),
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fpu = r.core.fpu.map(_.copy(divSqrt = false))))
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}
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})
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class WithNonblockingL1(nMSHRs: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nMSHRs = nMSHRs)))
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}
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})
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class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(nBreakpoints = hwbp))
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}
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})
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class WithRoccExample extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(rocc =
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Seq(
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RoCCParams(
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opcodes = OpcodeSet.custom0,
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generator = (p: Parameters) => {
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val accumulator = LazyModule(new AccumulatorExample()(p))
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accumulator}),
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RoCCParams(
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opcodes = OpcodeSet.custom1,
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generator = (p: Parameters) => {
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val translator = LazyModule(new TranslatorExample()(p))
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translator},
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nPTWPorts = 1),
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RoCCParams(
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opcodes = OpcodeSet.custom2,
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generator = (p: Parameters) => {
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val counter = LazyModule(new CharacterCountExample()(p))
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counter
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})
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))
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}
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})
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class WithDefaultBtb extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(btb = Some(BTBParams()))
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}
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})
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class WithFastMulDiv extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(mulDiv = Some(
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MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)
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)))}
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})
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class WithoutMulDiv extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(mulDiv = None))
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}
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})
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class WithoutFPU extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(fpu = None))
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}
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})
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class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(divSqrt = false))))
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}
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})
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class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
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case BootROMParams => up(BootROMParams, site).copy(contentFileName = bootROMFile)
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})
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class WithSynchronousRocketTiles extends Config((site, here, up) => {
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case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
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r.copy(crossingType = SynchronousCrossing())
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}
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})
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class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
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case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
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r.copy(crossingType = AsynchronousCrossing(depth, sync))
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}
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})
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class WithRationalRocketTiles extends Config((site, here, up) => {
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case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
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r.copy(crossingType = RationalCrossing())
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}
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})
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class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
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case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
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case ExtIn => up(ExtIn, site).copy(beatBytes = dataBits/8)
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})
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class WithJtagDTM extends Config ((site, here, up) => {
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case IncludeJtagDTM => true
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})
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class WithNoPeripheryArithAMO extends Config ((site, here, up) => {
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(arithmetic = false)
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})
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class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => {
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(beatBytes = nBits/8)
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})
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class WithoutTLMonitors extends Config ((site, here, up) => {
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case MonitorsEnabled => false
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})
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class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
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case NExtTopInterrupts => nExtInts
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})
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class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
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case BankedL2Key => up(BankedL2Key, site).copy(nMemoryChannels = n)
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})
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class WithExtMemSize(n: Long) extends Config((site, here, up) => {
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case ExtMem => up(ExtMem, site).copy(size = n)
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})
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class WithDTS(model: String, compat: Seq[String]) extends Config((site, here, up) => {
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case DTSModel => model
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case DTSCompat => compat
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})
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class WithTimebase(hertz: BigInt) extends Config((site, here, up) => {
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case DTSTimebase => hertz
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})
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