249 lines
8.4 KiB
Scala
249 lines
8.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package diplomacy
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import Chisel._
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import scala.math.max
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/** Options for memory regions */
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object RegionType {
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sealed trait T
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case object CACHED extends T
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case object TRACKED extends T
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case object UNCACHED extends T
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case object PUT_EFFECTS extends T
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case object GET_EFFECTS extends T // GET_EFFECTS => PUT_EFFECTS
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val cases = Seq(CACHED, TRACKED, UNCACHED, PUT_EFFECTS, GET_EFFECTS)
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}
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// A non-empty half-open range; [start, end)
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case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
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{
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require (start >= 0, s"Ids cannot be negative, but got: $start.")
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require (start < end, "Id ranges cannot be empty.")
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def compare(x: IdRange) = {
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val primary = (this.start - x.start).signum
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val secondary = (x.end - this.end).signum
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if (primary != 0) primary else secondary
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}
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def overlaps(x: IdRange) = start < x.end && x.start < end
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def contains(x: IdRange) = start <= x.start && x.end <= end
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// contains => overlaps (because empty is forbidden)
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def contains(x: Int) = start <= x && x < end
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def contains(x: UInt) =
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if (start+1 == end) { UInt(start) === x }
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else if (isPow2(end-start) && ((end | start) & (end-start-1)) == 0)
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{ ~(~(UInt(start) ^ x) | UInt(end-start-1)) === UInt(0) }
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else { UInt(start) <= x && x < UInt(end) }
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def shift(x: Int) = IdRange(start+x, end+x)
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def size = end - start
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def range = start until end
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}
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object IdRange
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{
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def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
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val ranges = s.sorted
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(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
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}
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}
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// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
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case class TransferSizes(min: Int, max: Int)
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{
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def this(x: Int) = this(x, x)
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require (min <= max, s"Min transfer $min > max transfer $max")
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require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
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require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
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require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
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require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
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def none = min == 0
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def contains(x: Int) = isPow2(x) && min <= x && x <= max
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def containsLg(x: Int) = contains(1 << x)
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def containsLg(x: UInt) =
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if (none) Bool(false)
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else if (min == max) { UInt(log2Ceil(min)) === x }
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else { UInt(log2Ceil(min)) <= x && x <= UInt(log2Ceil(max)) }
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def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
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def intersect(x: TransferSizes) =
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if (x.max < min || max < x.min) TransferSizes.none
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else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
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}
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object TransferSizes {
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def apply(x: Int) = new TransferSizes(x)
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val none = new TransferSizes(0)
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implicit def asBool(x: TransferSizes) = !x.none
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}
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// Use AddressSet instead -- this is just for pretty printing
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case class AddressRange(base: BigInt, size: BigInt) extends Ordered[AddressRange]
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{
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val end = base + size
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require (base >= 0, s"AddressRange base must be positive, got: $base")
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require (size > 0, s"AddressRange size must be > 0, got: $size")
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def compare(x: AddressRange) = {
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val primary = (this.base - x.base).signum
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val secondary = (x.size - this.size).signum
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if (primary != 0) primary else secondary
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}
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def contains(x: AddressRange) = base <= x.base && x.end <= end
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def union(x: AddressRange): Option[AddressRange] = {
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if (base > x.end || x.base > end) {
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None
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} else {
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val obase = if (base < x.base) base else x.base
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val oend = if (end > x.end) end else x.end
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Some(AddressRange(obase, oend-obase))
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}
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}
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}
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// AddressSets specify the address space managed by the manager
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// Base is the base address, and mask are the bits consumed by the manager
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// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
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// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
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case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
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{
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// Forbid misaligned base address (and empty sets)
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require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ($base, $mask)")
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require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
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// We do allow negative mask (=> ignore all high bits)
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def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
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def contains(x: UInt) = ((x ^ UInt(base)).zext() & SInt(~mask)) === SInt(0)
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// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
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def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
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// contains iff bitwise: x.mask => mask && contains(x.base)
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def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
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// The number of bytes to which the manager must be aligned
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def alignment = ((mask + 1) & ~mask)
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// Is this a contiguous memory range
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def contiguous = alignment == mask+1
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def finite = mask >= 0
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def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
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// Widen the match function to ignore all bits in imask
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def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
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// Return an AddressSet that only contains the addresses both sets contain
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def intersect(x: AddressSet): Option[AddressSet] = {
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if (!overlaps(x)) {
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None
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} else {
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val r_mask = mask & x.mask
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val r_base = base | x.base
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Some(AddressSet(r_base, r_mask))
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}
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}
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// AddressSets have one natural Ordering (the containment order, if contiguous)
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def compare(x: AddressSet) = {
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val primary = (this.base - x.base).signum // smallest address first
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val secondary = (x.mask - this.mask).signum // largest mask first
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if (primary != 0) primary else secondary
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}
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// We always want to see things in hex
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override def toString() = {
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if (mask >= 0) {
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"AddressSet(0x%x, 0x%x)".format(base, mask)
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} else {
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"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
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}
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}
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def toRanges = {
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require (finite, "Ranges cannot be calculated on infinite mask")
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val size = alignment
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val fragments = mask & ~(size-1)
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val bits = bitIndexes(fragments)
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(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
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val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
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AddressRange(off, size)
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}
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}
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}
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object AddressRange
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{
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def fromSets(seq: Seq[AddressSet]): Seq[AddressRange] = unify(seq.flatMap(_.toRanges))
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def unify(seq: Seq[AddressRange]): Seq[AddressRange] = {
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if (seq.isEmpty) return Nil
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val ranges = seq.sorted
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ranges.tail.foldLeft(Seq(ranges.head)) { case (head :: tail, x) =>
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head.union(x) match {
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case Some(z) => z :: tail
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case None => x :: head :: tail
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}
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}.reverse
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}
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}
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object AddressSet
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{
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def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
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if (size == 0) tail.reverse else {
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val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
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val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
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val step =
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if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
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maxSizeAlignment else maxBaseAlignment
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misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
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}
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}
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def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
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val n = seq.size
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val array = Array(seq:_*)
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var filter = Array.fill(n) { false }
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for (i <- 0 until n-1) { if (!filter(i)) {
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for (j <- i+1 until n) { if (!filter(j)) {
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val a = array(i)
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val b = array(j)
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if (a.mask == b.mask && isPow2(a.base ^ b.base)) {
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val c_base = a.base & ~(a.base ^ b.base)
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val c_mask = a.mask | (a.base ^ b.base)
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filter.update(j, true)
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array.update(i, AddressSet(c_base, c_mask))
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}
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}}
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}}
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val out = (array zip filter) flatMap { case (a, f) => if (f) None else Some(a) }
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if (out.size != n) unify(out) else out.toList
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}
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}
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case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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{
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require (depth >= 0, "Buffer depth must be >= 0")
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def isDefined = depth > 0
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def latency = if (isDefined && !flow) 1 else 0
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}
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object BufferParams
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{
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implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
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val default = BufferParams(2)
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val none = BufferParams(0)
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val flow = BufferParams(1, true, false)
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val pipe = BufferParams(1, false, true)
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}
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