384 lines
14 KiB
Scala
384 lines
14 KiB
Scala
package uncore.converters
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.constants._
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import cde.Parameters
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import scala.math.min
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class IdMapper(val inIdBits: Int, val outIdBits: Int,
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val forceMapping: Boolean = false)
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(implicit val p: Parameters) extends Module {
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val io = new Bundle {
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val req = new Bundle {
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val valid = Bool(INPUT)
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val ready = Bool(OUTPUT)
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val in_id = UInt(INPUT, inIdBits)
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val out_id = UInt(OUTPUT, outIdBits)
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}
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val resp = new Bundle {
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val valid = Bool(INPUT)
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val matches = Bool(OUTPUT)
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val out_id = UInt(INPUT, outIdBits)
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val in_id = UInt(OUTPUT, inIdBits)
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}
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}
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val maxInXacts = 1 << inIdBits
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if (inIdBits <= outIdBits && !forceMapping) {
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io.req.ready := Bool(true)
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io.req.out_id := io.req.in_id
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io.resp.matches := Bool(true)
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io.resp.in_id := io.resp.out_id
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} else {
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val nInXacts = 1 << inIdBits
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// No point in allowing more out xacts than in xacts
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val nOutXacts = min(1 << outIdBits, nInXacts)
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val out_id_free = Reg(init = Vec.fill(nOutXacts){Bool(true)})
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val in_id_free = Reg(init = Vec.fill(nInXacts){Bool(true)})
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val next_out_id = PriorityEncoder(out_id_free)
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val id_mapping = Reg(Vec(nOutXacts, UInt(0, inIdBits)))
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val req_fire = io.req.valid && io.req.ready
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when (req_fire) {
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out_id_free(io.req.out_id) := Bool(false)
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in_id_free(io.req.in_id) := Bool(false)
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id_mapping(io.req.out_id) := io.req.in_id
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}
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when (io.resp.valid) {
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out_id_free(io.resp.out_id) := Bool(true)
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in_id_free(io.resp.in_id) := Bool(true)
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}
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io.req.ready := out_id_free.reduce(_ || _) && in_id_free(io.req.in_id)
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io.req.out_id := next_out_id
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io.resp.in_id := id_mapping(io.resp.out_id)
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io.resp.matches := !out_id_free(io.resp.out_id)
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}
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}
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class NastiIOTileLinkIOConverterInfo(implicit p: Parameters) extends TLBundle()(p) {
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val addr_beat = UInt(width = tlBeatAddrBits)
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val subblock = Bool()
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}
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class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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with HasNastiParameters {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val nasti = new NastiIO
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}
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val dataBits = tlDataBits*tlDataBeats
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require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
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require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
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val has_data = io.tl.acquire.bits.hasData()
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val is_subblock = io.tl.acquire.bits.isSubBlockType()
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val is_multibeat = io.tl.acquire.bits.hasMultibeatData()
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val (tl_cnt_out, tl_wrap_out) = Counter(
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io.tl.acquire.fire() && is_multibeat, tlDataBeats)
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val get_valid = io.tl.acquire.valid && !has_data
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val put_valid = io.tl.acquire.valid && has_data
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// Reorder queue saves extra information needed to send correct
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// grant back to TL client
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val roqIdBits = min(tlClientXactIdBits, nastiXIdBits)
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val roq = Module(new ReorderQueue(
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new NastiIOTileLinkIOConverterInfo, roqIdBits))
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val get_id_mapper = Module(new IdMapper(tlClientXactIdBits, nastiXIdBits))
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val put_id_mapper = Module(new IdMapper(tlClientXactIdBits, nastiXIdBits))
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val get_id_ready = get_id_mapper.io.req.ready
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val put_id_mask = is_subblock || io.tl.acquire.bits.addr_beat === UInt(0)
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val put_id_ready = put_id_mapper.io.req.ready || !put_id_mask
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// For Get/GetBlock, make sure Reorder queue can accept new entry
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val get_helper = DecoupledHelper(
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get_valid,
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roq.io.enq.ready,
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io.nasti.ar.ready,
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get_id_ready)
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val w_inflight = Reg(init = Bool(false))
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val w_id_reg = Reg(init = UInt(0, nastiXIdBits))
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val w_id = Mux(w_inflight, w_id_reg, put_id_mapper.io.req.out_id)
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// For Put/PutBlock, make sure aw and w channel are both ready before
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// we send the first beat
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val aw_ready = w_inflight || io.nasti.aw.ready
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val put_helper = DecoupledHelper(
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put_valid,
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aw_ready,
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io.nasti.w.ready,
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put_id_ready)
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val (nasti_cnt_out, nasti_wrap_out) = Counter(
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io.nasti.r.fire() && !roq.io.deq.data.subblock, tlDataBeats)
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roq.io.enq.valid := get_helper.fire(roq.io.enq.ready)
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roq.io.enq.bits.tag := io.nasti.ar.bits.id
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roq.io.enq.bits.data.addr_beat := io.tl.acquire.bits.addr_beat
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roq.io.enq.bits.data.subblock := is_subblock
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roq.io.deq.valid := io.nasti.r.fire() && (nasti_wrap_out || roq.io.deq.data.subblock)
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roq.io.deq.tag := io.nasti.r.bits.id
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get_id_mapper.io.req.valid := get_helper.fire(get_id_ready)
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get_id_mapper.io.req.in_id := io.tl.acquire.bits.client_xact_id
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get_id_mapper.io.resp.valid := io.nasti.r.fire() && io.nasti.r.bits.last
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get_id_mapper.io.resp.out_id := io.nasti.r.bits.id
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put_id_mapper.io.req.valid := put_helper.fire(put_id_ready, put_id_mask)
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put_id_mapper.io.req.in_id := io.tl.acquire.bits.client_xact_id
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put_id_mapper.io.resp.valid := io.nasti.b.fire()
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put_id_mapper.io.resp.out_id := io.nasti.b.bits.id
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// Decompose outgoing TL Acquires into Nasti address and data channels
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io.nasti.ar.valid := get_helper.fire(io.nasti.ar.ready)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = get_id_mapper.io.req.out_id,
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addr = io.tl.acquire.bits.full_addr(),
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size = Mux(is_subblock,
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io.tl.acquire.bits.op_size(),
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UInt(log2Ceil(tlDataBytes))),
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len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1)))
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def mask_helper(all_inside_0: Seq[Bool], defsize: Int): (Seq[Bool], UInt, UInt) = {
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val len = all_inside_0.size
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if (len == 1) {
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(Seq(Bool(true)), UInt(0), UInt(defsize))
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} else {
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val sub_inside_0 = Seq.tabulate (len/2) { i => all_inside_0(2*i) && all_inside_0(2*i+1) }
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val (sub_outside_0, sub_offset, sub_size) = mask_helper(sub_inside_0, defsize+1)
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val all_outside_0 = Seq.tabulate (len) { i => sub_outside_0(i/2) && all_inside_0(i^1) }
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val odd_outside_0 = Seq.tabulate (len/2) { i => all_outside_0(2*i+1) }
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val odd_outside = odd_outside_0.reduce (_ || _)
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val all_outside = all_outside_0.reduce (_ || _)
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val offset = Cat(sub_offset, odd_outside)
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val size = Mux(all_outside, UInt(defsize), sub_size)
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(all_outside_0, offset, size)
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}
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}
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val all_inside_0 = (~io.tl.acquire.bits.wmask()).toBools
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val (_, put_offset, put_size) = mask_helper(all_inside_0, 0)
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io.nasti.aw.valid := put_helper.fire(aw_ready, !w_inflight)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = put_id_mapper.io.req.out_id,
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addr = io.tl.acquire.bits.full_addr() |
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Mux(is_multibeat, UInt(0), put_offset),
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size = Mux(is_multibeat, UInt(log2Ceil(tlDataBytes)), put_size),
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len = Mux(is_multibeat, UInt(tlDataBeats - 1), UInt(0)))
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io.nasti.w.valid := put_helper.fire(io.nasti.w.ready)
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io.nasti.w.bits := NastiWriteDataChannel(
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id = w_id,
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data = io.tl.acquire.bits.data,
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strb = Some(io.tl.acquire.bits.wmask()),
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last = Mux(w_inflight,
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tl_cnt_out === UInt(tlDataBeats - 1), !is_multibeat))
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io.tl.acquire.ready := Mux(has_data,
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put_helper.fire(put_valid),
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get_helper.fire(get_valid))
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when (!w_inflight && io.tl.acquire.fire() && is_multibeat) {
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w_inflight := Bool(true)
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w_id_reg := w_id
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}
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when (w_inflight) {
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when (tl_wrap_out) { w_inflight := Bool(false) }
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}
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// Aggregate incoming NASTI responses into TL Grants
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val (tl_cnt_in, tl_wrap_in) = Counter(
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io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats)
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val gnt_arb = Module(new LockingArbiter(new GrantToDst, 2,
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tlDataBeats, Some((gnt: GrantToDst) => gnt.hasMultibeatData())))
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io.tl.grant <> gnt_arb.io.out
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gnt_arb.io.in(0).valid := io.nasti.r.valid
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io.nasti.r.ready := gnt_arb.io.in(0).ready
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gnt_arb.io.in(0).bits := Grant(
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is_builtin_type = Bool(true),
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g_type = Mux(roq.io.deq.data.subblock,
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Grant.getDataBeatType, Grant.getDataBlockType),
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client_xact_id = get_id_mapper.io.resp.in_id,
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manager_xact_id = UInt(0),
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addr_beat = Mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in),
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data = io.nasti.r.bits.data)
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assert(!roq.io.deq.valid || roq.io.deq.matches,
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"TL -> NASTI converter ReorderQueue: NASTI tag error")
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assert(!gnt_arb.io.in(0).valid || get_id_mapper.io.resp.matches,
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"TL -> NASTI ID Mapper: NASTI tag error")
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gnt_arb.io.in(1).valid := io.nasti.b.valid
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io.nasti.b.ready := gnt_arb.io.in(1).ready
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gnt_arb.io.in(1).bits := Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.putAckType,
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client_xact_id = put_id_mapper.io.resp.in_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = Bits(0))
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assert(!gnt_arb.io.in(1).valid || put_id_mapper.io.resp.matches, "NASTI tag error")
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assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), "NASTI read error")
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assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), "NASTI write error")
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}
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class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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with HasNastiParameters {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val tl = new ClientUncachedTileLinkIO
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}
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val (s_idle :: s_put :: Nil) = Enum(Bits(), 2)
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val state = Reg(init = s_idle)
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private val blockOffset = tlByteAddrBits + tlBeatAddrBits
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val aw_req = Reg(new NastiWriteAddressChannel)
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val w_tl_id = Reg(io.tl.acquire.bits.client_xact_id)
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def is_singlebeat(chan: NastiAddressChannel): Bool =
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chan.len === UInt(0)
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def is_multibeat(chan: NastiAddressChannel): Bool =
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chan.len === UInt(tlDataBeats - 1) && chan.size === UInt(log2Up(tlDataBytes))
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def nasti_addr_block(chan: NastiAddressChannel): UInt =
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chan.addr(nastiXAddrBits - 1, blockOffset)
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def nasti_addr_beat(chan: NastiAddressChannel): UInt =
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chan.addr(blockOffset - 1, tlByteAddrBits)
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def nasti_addr_byte(chan: NastiAddressChannel): UInt =
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chan.addr(tlByteAddrBits - 1, 0)
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def size_mask(size: UInt): UInt =
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(UInt(1) << (UInt(1) << size)) - UInt(1)
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def nasti_wmask(aw: NastiWriteAddressChannel, w: NastiWriteDataChannel): UInt = {
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val base = w.strb & size_mask(aw.size)
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val addr_byte = nasti_addr_byte(aw)
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w.strb & (size_mask(aw.size) << addr_byte)
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}
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def tl_last(gnt: GrantMetadata): Bool =
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!gnt.hasMultibeatData() || gnt.addr_beat === UInt(tlDataBeats - 1)
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def tl_b_grant(gnt: GrantMetadata): Bool =
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gnt.g_type === Grant.putAckType
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assert(!io.nasti.ar.valid ||
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is_singlebeat(io.nasti.ar.bits) || is_multibeat(io.nasti.ar.bits),
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"NASTI read transaction cannot convert to TileLInk")
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assert(!io.nasti.aw.valid ||
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is_singlebeat(io.nasti.aw.bits) || is_multibeat(io.nasti.aw.bits),
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"NASTI write transaction cannot convert to TileLInk")
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val put_count = Reg(init = UInt(0, tlBeatAddrBits))
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val get_id_mapper = Module(new IdMapper(nastiXIdBits, tlClientXactIdBits, true))
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val put_id_mapper = Module(new IdMapper(nastiXIdBits, tlClientXactIdBits, true))
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when (io.nasti.aw.fire()) {
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aw_req := io.nasti.aw.bits
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w_tl_id := put_id_mapper.io.req.out_id
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state := s_put
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}
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when (io.nasti.w.fire()) {
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put_count := put_count + UInt(1)
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when (io.nasti.w.bits.last) {
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put_count := UInt(0)
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state := s_idle
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}
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}
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val get_acquire = Mux(is_multibeat(io.nasti.ar.bits),
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GetBlock(
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client_xact_id = get_id_mapper.io.req.out_id,
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addr_block = nasti_addr_block(io.nasti.ar.bits)),
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Get(
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client_xact_id = get_id_mapper.io.req.out_id,
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addr_block = nasti_addr_block(io.nasti.ar.bits),
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addr_beat = nasti_addr_beat(io.nasti.ar.bits),
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addr_byte = nasti_addr_byte(io.nasti.ar.bits),
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operand_size = io.nasti.ar.bits.size,
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alloc = Bool(false)))
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val put_acquire = Mux(is_multibeat(aw_req),
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PutBlock(
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client_xact_id = w_tl_id,
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addr_block = nasti_addr_block(aw_req),
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addr_beat = put_count,
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data = io.nasti.w.bits.data,
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wmask = Some(io.nasti.w.bits.strb)),
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Put(
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client_xact_id = w_tl_id,
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addr_block = nasti_addr_block(aw_req),
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addr_beat = nasti_addr_beat(aw_req),
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data = io.nasti.w.bits.data,
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wmask = Some(nasti_wmask(aw_req, io.nasti.w.bits))))
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val get_helper = DecoupledHelper(
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io.nasti.ar.valid,
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get_id_mapper.io.req.ready,
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io.tl.acquire.ready)
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get_id_mapper.io.req.valid := get_helper.fire(
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get_id_mapper.io.req.ready, state === s_idle)
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get_id_mapper.io.req.in_id := io.nasti.ar.bits.id
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get_id_mapper.io.resp.out_id := io.tl.grant.bits.client_xact_id
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get_id_mapper.io.resp.valid := io.nasti.r.fire() && io.nasti.r.bits.last
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val aw_ok = (state === s_idle && !io.nasti.ar.valid)
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put_id_mapper.io.req.valid := aw_ok && io.nasti.aw.valid
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put_id_mapper.io.req.in_id := io.nasti.aw.bits.id
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put_id_mapper.io.resp.out_id := io.tl.grant.bits.client_xact_id
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put_id_mapper.io.resp.valid := io.nasti.b.fire()
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io.tl.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.tl.acquire.valid := get_helper.fire(io.tl.acquire.ready, state === s_idle) ||
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(state === s_put && io.nasti.w.valid)
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io.nasti.ar.ready := get_helper.fire(io.nasti.ar.valid, state === s_idle)
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io.nasti.aw.ready := aw_ok && put_id_mapper.io.req.ready
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io.nasti.w.ready := (state === s_put && io.tl.acquire.ready)
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val nXacts = tlMaxClientXacts * tlMaxClientsPerPort
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io.nasti.b.valid := io.tl.grant.valid && tl_b_grant(io.tl.grant.bits)
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io.nasti.b.bits := NastiWriteResponseChannel(
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id = put_id_mapper.io.resp.in_id)
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assert(!io.nasti.b.valid || put_id_mapper.io.resp.matches,
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"Put ID does not match")
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io.nasti.r.valid := io.tl.grant.valid && !tl_b_grant(io.tl.grant.bits)
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io.nasti.r.bits := NastiReadDataChannel(
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id = get_id_mapper.io.resp.in_id,
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data = io.tl.grant.bits.data,
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last = tl_last(io.tl.grant.bits))
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assert(!io.nasti.r.valid || get_id_mapper.io.resp.matches,
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"Get ID does not match")
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io.tl.grant.ready := Mux(tl_b_grant(io.tl.grant.bits),
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io.nasti.b.ready, io.nasti.r.ready)
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}
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