19 lines
404 B
Verilog
19 lines
404 B
Verilog
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/* This blackbox is needed by
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* Chisel in order to do type conversion.
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* It may be useful for some synthesis flows
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* as well which require special
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* flagging on conversion from data to clock.
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*/
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module SignalToClock (
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output clock_out,
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input signal_in
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);
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assign clock_out = signal_in;
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endmodule // SignalToClock
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