224 lines
7.3 KiB
Scala
224 lines
7.3 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import Util._
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import Node._
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import uncore._
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case object NBTBEntries extends Field[Int]
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case object NRAS extends Field[Int]
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abstract trait BTBParameters extends UsesParameters {
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val vaddrBits = params(VAddrBits)
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val matchBits = params(PgIdxBits)
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val entries = params(NBTBEntries)
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val nRAS = params(NRAS)
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val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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class RAS(nras: Int) {
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def push(addr: UInt): Unit = {
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when (count < nras) { count := count + 1 }
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val nextPos = Mux(Bool(isPow2(nras)) || pos > 0, pos+1, UInt(0))
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stack(nextPos) := addr
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pos := nextPos
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}
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def peek: UInt = stack(pos)
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def pop: Unit = when (!isEmpty) {
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count := count - 1
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pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
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}
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def clear: Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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private val count = Reg(init=UInt(0,log2Up(nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(nras)))
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private val stack = Vec.fill(nras){Reg(UInt())}
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}
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class BHTResp extends Bundle with BTBParameters {
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val index = UInt(width = log2Up(nBHT).max(1))
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val value = UInt(width = 2)
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}
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class BHT(nbht: Int) {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt): BHTResp = {
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val res = new BHTResp
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res.index := addr(nbhtbits+1,2) ^ history
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res.value := table(res.index)
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res
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}
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def update(d: BHTResp, taken: Bool): Unit = {
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table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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history := Cat(taken, history(nbhtbits-1,1))
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}
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private val table = Mem(UInt(width = 2), nbht)
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val history = Reg(UInt(width = nbhtbits))
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}
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class BTBUpdate extends Bundle with BTBParameters {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val returnAddr = UInt(width = vaddrBits)
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val taken = Bool()
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val isJump = Bool()
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val isCall = Bool()
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val isReturn = Bool()
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val incorrectTarget = Bool()
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}
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class BTBResp extends Bundle with BTBParameters {
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val taken = Bool()
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val target = UInt(width = vaddrBits)
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val entry = UInt(width = opaqueBits)
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val bht = new BHTResp
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}
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// fully-associative branch target buffer
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class BTB extends Module with BTBParameters {
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val io = new Bundle {
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val req = UInt(INPUT, vaddrBits)
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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}
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val idxValid = Reg(init=UInt(0, entries))
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val idxs = Mem(UInt(width=matchBits), entries)
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val idxPages = Mem(UInt(width=log2Up(nPages)), entries)
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val tgts = Mem(UInt(width=matchBits), entries)
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val tgtPages = Mem(UInt(width=log2Up(nPages)), entries)
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val pages = Mem(UInt(width=vaddrBits-matchBits), nPages)
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val pageValid = Reg(init=UInt(0, nPages))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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val useRAS = Reg(UInt(width = entries))
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val isJump = Reg(UInt(width = entries))
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private def page(addr: UInt) = addr >> matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid
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}
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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val idx = addr(matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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idxValid & idxMatch & idxPageMatch
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}
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val update = Pipe(io.update)
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val update_target = io.req
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val pageHit = pageMatch(io.req)
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val hits = tagMatch(io.req, pageHit)
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val updatePageHit = pageMatch(update.bits.pc)
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val updateHits = tagMatch(update.bits.pc, updatePageHit)
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private var lfsr = LFSR16(update.valid)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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val updateHit = update.bits.prediction.valid
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val updateValid = update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && update.bits.incorrectTarget
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
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val idxPageRepl = UInt()
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, nPages)._1)
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when (update.valid && !(updateValid && !updateTarget)) {
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val nextRepl = Counter(!updateHit && updateValid, entries)._1
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val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := updateValid
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when (updateTarget) {
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assert(io.req === update.bits.target, "BTB request != I$ target")
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idxs(waddr) := update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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useRAS(waddr) := update.bits.isReturn
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isJump(waddr) := update.bits.isJump
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}
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require(nPages % 2 == 0)
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val idxWritesEven = (idxPageUpdateOH & Fill(nPages/2, UInt(1,2))).orR
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
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for (i <- i until nPages by mod)
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when (en && pageReplEn(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(update_target), page(update.bits.pc)))
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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}
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when (io.invalidate) {
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idxValid := 0
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pageValid := 0
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}
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io.resp.valid := hits.orR
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.entry := OHToUInt(hits)
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val res = bht.get(io.req)
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when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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}
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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val doPeek = Mux1H(hits, useRAS)
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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when (io.update.valid) {
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when (io.update.bits.isCall) {
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ras.push(io.update.bits.returnAddr)
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when (doPeek) {
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io.resp.bits.target := io.update.bits.returnAddr
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}
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}.elsewhen (io.update.bits.isReturn && io.update.bits.prediction.valid) {
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ras.pop
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}
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}
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when (io.invalidate) { ras.clear }
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}
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}
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