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rocket-chip/csrc
Palmer Dabbelt 926efd0cab Allow the number of memory channels to be picked at runtime
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
..
comlog.cc cleaner/faster comlog without linear search 2015-09-15 17:19:29 -07:00
emulator.cc add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
float_fix.cc remove bugs from float_fix 2015-09-23 16:11:47 -07:00
htif_emulator.h Allow the number of memory channels to be picked at runtime 2016-02-17 15:23:30 -08:00
mm_dramsim2.cc Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
mm_dramsim2.h Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
mm.cc use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
mm.h use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
vcs_main.rocketTestHarness.cc Allow the number of memory channels to be picked at runtime 2016-02-17 15:23:30 -08:00
vcs_main.ZscaleTestHarness.cc Fix zscale testing 2015-12-01 17:31:48 -08:00