4c595d175c
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
146 lines
4.1 KiB
Scala
146 lines
4.1 KiB
Scala
// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.util
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import Chisel._
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import freechips.rocketchip.config.Parameters
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/** A generalized locking RR arbiter that addresses the limitations of the
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* version in the Chisel standard library */
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abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false)
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extends Module {
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val io = new Bundle {
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val in = Vec(arbN, Decoupled(typ.cloneType)).flip
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val out = Decoupled(typ.cloneType)
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}
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def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = {
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val n = norm.size
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Vec.tabulate(n) { i =>
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Mux(rot < UInt(n - i), norm(UInt(i) + rot), norm(rot - UInt(n - i)))
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}
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}
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val lockIdx = Reg(init = UInt(0, log2Up(arbN)))
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val locked = Reg(init = Bool(false))
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val choice = if (rr) {
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PriorityMux(
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rotateLeft(Vec(io.in.map(_.valid)), lockIdx + UInt(1)),
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rotateLeft(Vec((0 until arbN).map(UInt(_))), lockIdx + UInt(1)))
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} else {
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PriorityEncoder(io.in.map(_.valid))
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}
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val chosen = Mux(locked, lockIdx, choice)
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for (i <- 0 until arbN) {
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io.in(i).ready := io.out.ready && chosen === UInt(i)
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}
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io.out.valid := io.in(chosen).valid
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io.out.bits := io.in(chosen).bits
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}
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/** This locking arbiter determines when it is safe to unlock
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* by peeking at the data */
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class HellaPeekingArbiter[T <: Data](
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typ: T, arbN: Int,
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canUnlock: T => Bool,
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needsLock: Option[T => Bool] = None,
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rr: Boolean = false)
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extends HellaLockingArbiter(typ, arbN, rr) {
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def realNeedsLock(data: T): Bool =
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needsLock.map(_(data)).getOrElse(Bool(true))
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when (io.out.fire()) {
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when (!locked && realNeedsLock(io.out.bits)) {
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lockIdx := choice
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locked := Bool(true)
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}
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// the unlock statement takes precedent
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when (canUnlock(io.out.bits)) {
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locked := Bool(false)
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}
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}
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}
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/** This arbiter determines when it is safe to unlock by counting transactions */
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class HellaCountingArbiter[T <: Data](
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typ: T, arbN: Int, count: Int,
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val needsLock: Option[T => Bool] = None,
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rr: Boolean = false)
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extends HellaLockingArbiter(typ, arbN, rr) {
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def realNeedsLock(data: T): Bool =
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needsLock.map(_(data)).getOrElse(Bool(true))
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// if count is 1, you should use a non-locking arbiter
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require(count > 1, "CountingArbiter cannot have count <= 1")
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val lock_ctr = Counter(count)
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when (io.out.fire()) {
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when (!locked && realNeedsLock(io.out.bits)) {
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lockIdx := choice
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locked := Bool(true)
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lock_ctr.inc()
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}
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when (locked) {
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when (lock_ctr.inc()) { locked := Bool(false) }
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}
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}
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}
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/** This arbiter preserves the order of responses */
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class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)
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(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val in_req = Vec(n, Decoupled(reqTyp)).flip
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val in_resp = Vec(n, Decoupled(respTyp))
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val out_req = Decoupled(reqTyp)
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val out_resp = Decoupled(respTyp).flip
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}
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if (n > 1) {
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val route_q = Module(new Queue(UInt(width = log2Up(n)), 2))
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val req_arb = Module(new RRArbiter(reqTyp, n))
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req_arb.io.in <> io.in_req
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val req_helper = DecoupledHelper(
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req_arb.io.out.valid,
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route_q.io.enq.ready,
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io.out_req.ready)
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io.out_req.bits := req_arb.io.out.bits
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io.out_req.valid := req_helper.fire(io.out_req.ready)
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route_q.io.enq.bits := req_arb.io.chosen
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route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready)
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req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid)
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val resp_sel = route_q.io.deq.bits
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val resp_ready = io.in_resp(resp_sel).ready
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val resp_helper = DecoupledHelper(
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resp_ready,
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route_q.io.deq.valid,
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io.out_resp.valid)
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val resp_valid = resp_helper.fire(resp_ready)
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for (i <- 0 until n) {
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io.in_resp(i).bits := io.out_resp.bits
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io.in_resp(i).valid := resp_valid && resp_sel === UInt(i)
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}
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route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid)
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io.out_resp.ready := resp_helper.fire(io.out_resp.valid)
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} else {
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io.out_req <> io.in_req.head
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io.in_resp.head <> io.out_resp
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}
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}
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