This website requires JavaScript.
Explore
Help
Sign In
riscv
/
rocket-chip
Watch
1
Star
0
Fork
0
You've already forked rocket-chip
Code
Releases
Activity
rocket-chip
/
src
History
Andrew Waterman
3951e57789
Force each TLB entry into its own clock-gate group
...
This ameliorates a PMP critical path. I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
..
main
/scala
Force each TLB entry into its own clock-gate group
2017-03-24 16:39:52 -07:00