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rocket-chip/src
Andrew Waterman 3951e57789 Force each TLB entry into its own clock-gate group
This ameliorates a PMP critical path.

I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
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main/scala Force each TLB entry into its own clock-gate group 2017-03-24 16:39:52 -07:00