118 lines
4.2 KiB
Scala
118 lines
4.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import rocket._
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import tile._
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import uncore.tilelink2._
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sealed trait ClockCrossing
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case object Synchronous extends ClockCrossing
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case object Rational extends ClockCrossing
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case class Asynchronous(depth: Int, sync: Int = 2) extends ClockCrossing
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case object RocketTilesKey extends Field[Seq[RocketTileParams]]
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case object RocketCrossing extends Field[ClockCrossing]
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trait HasRocketTiles extends CoreplexRISCVPlatform {
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val module: HasRocketTilesModule
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private val crossing = p(RocketCrossing)
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private val configs = p(RocketTilesKey)
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// TODO: hack to fix deduplication; see PR https://github.com/ucb-bar/berkeley-hardfloat/pull/14
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hardfloat.consts
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val rocketWires: Seq[HasRocketTilesBundle => Unit] = configs.zipWithIndex.map { case (c, i) =>
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val pWithExtra = p.alterPartial {
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case TileKey => c
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case BuildRoCC => c.rocc
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case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
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case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
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}
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// Hack debug interrupt into a node (future debug module should use diplomacy)
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val debugNode = IntInternalInputNode(IntSourcePortSimple())
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val intBar = LazyModule(new IntXbar)
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intBar.intnode := debugNode
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intBar.intnode := clint.intnode // msip+mtip
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intBar.intnode := plic.intnode // meip
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if (c.core.useVM) intBar.intnode := plic.intnode // seip
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crossing match {
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case Synchronous => {
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val tile = LazyModule(new RocketTile(c, i)(pWithExtra))
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val buffer = LazyModule(new TLBuffer)
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val fixer = LazyModule(new TLFIFOFixer)
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buffer.node :=* tile.masterNode
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fixer.node :=* buffer.node
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l1tol2.node :=* fixer.node
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tile.slaveNode :*= cbus.node
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tile.intNode := intBar.intnode
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(io: HasRocketTilesBundle) => {
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// leave clock as default (simpler for hierarchical PnR)
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tile.module.io.hartid := UInt(i)
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tile.module.io.resetVector := io.resetVector
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debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
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}
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}
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case Asynchronous(depth, sync) => {
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val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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val fixer = LazyModule(new TLFIFOFixer)
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sink.node :=* wrapper.masterNode
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fixer.node :=* sink.node
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l1tol2.node :=* fixer.node
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wrapper.slaveNode :*= source.node
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wrapper.intNode := intBar.intnode
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source.node :*= cbus.node
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(io: HasRocketTilesBundle) => {
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wrapper.module.clock := io.tcrs(i).clock
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wrapper.module.reset := io.tcrs(i).reset
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wrapper.module.io.hartid := UInt(i)
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wrapper.module.io.resetVector := io.resetVector
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debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
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}
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}
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case Rational => {
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val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
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val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
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val source = LazyModule(new TLRationalCrossingSource)
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val fixer = LazyModule(new TLFIFOFixer)
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sink.node :=* wrapper.masterNode
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fixer.node :=* sink.node
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l1tol2.node :=* fixer.node
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wrapper.slaveNode :*= source.node
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wrapper.intNode := intBar.intnode
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source.node :*= cbus.node
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(io: HasRocketTilesBundle) => {
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wrapper.module.clock := io.tcrs(i).clock
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wrapper.module.reset := io.tcrs(i).reset
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wrapper.module.io.hartid := UInt(i)
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wrapper.module.io.resetVector := io.resetVector
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debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
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}
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}
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}
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}
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}
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trait HasRocketTilesBundle extends CoreplexRISCVPlatformBundle {
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val outer: HasRocketTiles
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val tcrs = Vec(p(RocketTilesKey).size, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait HasRocketTilesModule extends CoreplexRISCVPlatformModule {
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val outer: HasRocketTiles
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val io: HasRocketTilesBundle
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outer.rocketWires.foreach { _(io) }
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}
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