77a0f76289
* debug: Clean up Debug TransportModule synchronizer With async reset async queues, I feel its safe/cleaner to remove the one-off "AsyncMailbox verilog black-box and use the common primitive. I also added some comments about correct usage of this block. Probably the 'TRST' signal should be renamed to make it less confusing, as it requires some processing of the real JTAG 'TRST' signal.
252 lines
11 KiB
Makefile
252 lines
11 KiB
Makefile
# The default target, which runs all regression targets.
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regression: vsim-regression emulator-regression
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# Regression targets for the various simulators.
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%-regression: %-asm-tests %-bmark-tests
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# Some targets can run torture
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vsim-regression: vsim-torture
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emulator-regression: emulator-torture
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# The torture configuration to use
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TORTURE_CONFIG ?= default
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# The top-level directory that contains rocket-chip
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TOP ?= ..
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# The hash of the tools that we're using
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TOOLS_HASH ?= $(shell git -C $(TOP) ls-tree HEAD -- riscv-tools | xargs echo | cut -d' ' -f3)
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$(info Using riscv-tools of $(TOOLS_HASH))
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# The directory that the tools get built into.
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RISCV ?= install/$(TOOLS_HASH)
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# Torture saves the failing tests into a directory, which defaults to just somehing inside the regressions directory.
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TORTURE_SAVE_DIR ?= torture-failures
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# Include top-level makefrag for options like rocketchip_addons
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include $(TOP)/Makefrag
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# Removes all the build stamps from the current config
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.PHONY: clean
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clean:
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rm -rf stamps $(abspath $(RISCV))
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$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/vsim) clean
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$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/emulator) clean
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ifeq ($(SUITE),)
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$(error Set SUITE to the regression suite you want to run)
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endif
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ifeq ($(SUITE),RocketSuite)
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PROJECT=rocketchip
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CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
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endif
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ifeq ($(SUITE),GroundtestSuite)
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PROJECT=groundtest
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CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
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BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
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ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
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endif
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ifeq ($(SUITE),UnittestSuite)
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PROJECT=unittest
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CONFIGS=JunctionsUnitTestConfig UncoreUnitTestConfig
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endif
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ifeq ($(SUITE), JtagDtmSuite)
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CONFIGS_32=WithJtagDTM_DefaultRV32Config
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CONFIGS_64=WithJtagDTM_DefaultConfig
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CONFIGS += $(CONFIGS_32)
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CONFIGS += $(CONFIGS_64)
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endif
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# These are the named regression targets. While it's expected you run them in
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# this order, since there's dependencies for everything it doesn't actually
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# matter. They're here to make running the various targets from the
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# commandline a bit cleaner.
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submodules: stamps/other-submodules.stamp
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tools: $(RISCV)/install.stamp
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EMU_DEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-debug.stamp)
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EMU_NDEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-ndebug.stamp)
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EMU_ASM_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-asm-tests.stamp)
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EMU_BMARK_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-bmark-tests.stamp)
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EMU_REGRESSION_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-regression-tests.stamp)
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EMU_TORTURE_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-torture-$(TORTURE_CONFIG).stamp)
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emulator-debug: $(EMU_DEBUG_STAMPS)
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emulator-ndebug: $(EMU_NDEBUG_STAMPS)
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emulator-asm-tests: $(EMU_ASM_TEST_STAMPS)
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emulator-bmark-tests: $(EMU_BMARK_TEST_STAMPS)
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emulator-regression-tests: $(EMU_REGRESSION_TEST_STAMPS)
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emulator-torture: $(EMU_TORTURE_STAMPS)
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VSIM_VERILOG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-verilog.stamp)
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VSIM_DEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-debug.stamp)
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VSIM_NDEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-ndebug.stamp)
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VSIM_ASM_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-asm-tests.stamp)
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VSIM_BMARK_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-bmark-tests.stamp)
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VSIM_REGRESSION_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-regression-tests.stamp)
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VSIM_TORTURE_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/vsim-torture-$(TORTURE_CONFIG).stamp)
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vsim-verilog: $(VSIM_VERILOG_STAMPS)
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vsim-debug: $(VSIM_DEBUG_STAMPS)
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vsim-ndebug: $(VSIM_NDEBUG_STAMPS)
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vsim-asm-tests: $(VSIM_ASM_TEST_STAMPS)
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vsim-bmark-tests: $(VSIM_BMARK_TEST_STAMPS)
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vsim-regression-tests: $(VSIM_REGRESSION_TEST_STAMPS)
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vsim-torture: $(VSIM_TORTURE_STAMPS)
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submodule_names = chisel3 context-dependent-environments firrtl torture hardfloat $(ROCKETCHIP_ADDONS)
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# Checks out all the rocket-chip submodules
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stamps/other-submodules.stamp:
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mkdir -p $(dir $@)
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git -C $(abspath $(TOP)) submodule update --init --recursive $(submodule_names)
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date > $@
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$(RISCV)/install.stamp:
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mkdir -p $(dir $@)
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git -C $(abspath $(TOP)) submodule update --init riscv-tools
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rm -f $(abspath $(TOP))/riscv-tools/.travis.yml
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-gnu-toolchain
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-isa-sim
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-fesvr
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-opcodes
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-pk
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-tests
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+cd $(abspath $(TOP))/riscv-tools; RISCV=$(abspath $(RISCV)) ./build.sh
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date > $@
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# Builds the various simulators
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stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
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date > $@
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stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
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date > $@
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stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
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date > $@
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stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
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date > $@
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stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
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date > $@
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stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
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date > $@
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# Runs tests on one of the simulators
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stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
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date > $@
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stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
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date > $@
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stamps/%/emulator-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
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date > $@
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stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
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date > $@
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stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
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date > $@
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stamps/%/vsim-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
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date > $@
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# The torture tests run subtly differently on the different targets, so they
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# don't have pattern rules like everything else does.
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stamps/%/vsim-torture-$(TORTURE_CONFIG).stamp: stamps/%/vsim-debug.stamp stamps/%/vsim-ndebug.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/torture rnight RTL_CONFIG=$* RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10"
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date > $@
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stamps/%/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/%/emulator-debug.stamp stamps/%/emulator-ndebug.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/torture cnight RTL_CONFIG=$* RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10"
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date > $@
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# Targets for JTAG DTM full-chain simulation
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OPENOCD_HEAD ?= riscv
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OPENOCD_INSTALL ?= $(abspath $(TOP))/openocd-install
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OPENOCD_VERSION = $(shell git ls-remote http://github.com/sifive/openocd.git $(OPENOCD_HEAD) | awk '{print $$1}')
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OPENOCD_DIR = $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/
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$(OPENOCD_DIR)/bin/openocd:
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rm -rf openocd
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git clone http://github.com/sifive/openocd.git
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cd openocd ; \
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git checkout $(OPENOCD_VERSION) ; \
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./bootstrap ; \
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./configure --enable-jtag-vpi --prefix=$(OPENOCD_INSTALL)_$(OPENOCD_VERSION) ; \
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make ; \
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make install
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install_openocd: $(OPENOCD_DIR)/bin/openocd
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# If this is defined empty, then all tests would run.
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# Running a list of tests is not supported.
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JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
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stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--cmd="$(OPENOCD_DIR)/bin/openocd \
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--s $(OPENOCD_DIR)/share/openocd/scripts" \
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--freedom-e300-sim \
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$(JTAG_DTM_TEST)
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date > $@
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stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \
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--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
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--freedom-u500-sim \
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$(JTAG_DTM_TEST)
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date > $@
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JTAG_DTM_32_TEST_STAMPS=$(foreach config,$(CONFIGS_32),stamps/$(config)/jtag-dtm-32-$(JTAG_DTM_TEST).stamp)
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JTAG_DTM_64_TEST_STAMPS=$(foreach config,$(CONFIGS_64),stamps/$(config)/jtag-dtm-64-$(JTAG_DTM_TEST).stamp)
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jtag-dtm-tests-32 : $(JTAG_DTM_32_TEST_STAMPS)
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jtag-dtm-tests-64 : $(JTAG_DTM_64_TEST_STAMPS)
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# Targets for JTAG DTM full-chain simulation
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jtag-dtm-regression: jtag-dtm-tests-32 jtag-dtm-tests-64
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