573 lines
19 KiB
Scala
573 lines
19 KiB
Scala
/// See LICENSE for license details.
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package junctions
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import Chisel._
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import scala.math.max
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import scala.collection.mutable.ArraySeq
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import cde.{Parameters, Field}
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case object NastiKey extends Field[NastiParameters]
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case class NastiParameters(dataBits: Int, addrBits: Int, idBits: Int)
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trait HasNastiParameters {
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implicit val p: Parameters
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val external = p(NastiKey)
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val nastiXDataBits = external.dataBits
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val nastiWStrobeBits = nastiXDataBits / 8
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val nastiXAddrBits = external.addrBits
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val nastiWIdBits = external.idBits
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val nastiRIdBits = external.idBits
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val nastiXIdBits = max(nastiWIdBits, nastiRIdBits)
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val nastiXUserBits = 1
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val nastiAWUserBits = nastiXUserBits
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val nastiWUserBits = nastiXUserBits
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val nastiBUserBits = nastiXUserBits
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val nastiARUserBits = nastiXUserBits
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val nastiRUserBits = nastiXUserBits
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val nastiXLenBits = 8
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val nastiXSizeBits = 3
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val nastiXBurstBits = 2
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val nastiXCacheBits = 4
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val nastiXProtBits = 3
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val nastiXQosBits = 4
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val nastiXRegionBits = 4
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val nastiXRespBits = 2
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def bytesToXSize(bytes: UInt) = MuxLookup(bytes, UInt("b111"), Array(
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UInt(1) -> UInt(0),
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UInt(2) -> UInt(1),
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UInt(4) -> UInt(2),
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UInt(8) -> UInt(3),
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UInt(16) -> UInt(4),
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UInt(32) -> UInt(5),
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UInt(64) -> UInt(6),
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UInt(128) -> UInt(7)))
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}
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abstract class NastiModule(implicit val p: Parameters) extends Module
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with HasNastiParameters
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abstract class NastiBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasNastiParameters
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abstract class NastiChannel(implicit p: Parameters) extends NastiBundle()(p)
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abstract class NastiMasterToSlaveChannel(implicit p: Parameters) extends NastiChannel()(p)
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abstract class NastiSlaveToMasterChannel(implicit p: Parameters) extends NastiChannel()(p)
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trait HasNastiMetadata extends HasNastiParameters {
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val addr = UInt(width = nastiXAddrBits)
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val len = UInt(width = nastiXLenBits)
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val size = UInt(width = nastiXSizeBits)
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val burst = UInt(width = nastiXBurstBits)
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val lock = Bool()
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val cache = UInt(width = nastiXCacheBits)
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val prot = UInt(width = nastiXProtBits)
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val qos = UInt(width = nastiXQosBits)
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val region = UInt(width = nastiXRegionBits)
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}
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trait HasNastiData extends HasNastiParameters {
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val data = UInt(width = nastiXDataBits)
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val last = Bool()
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}
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class NastiIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
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val aw = Decoupled(new NastiWriteAddressChannel)
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val w = Decoupled(new NastiWriteDataChannel)
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val b = Decoupled(new NastiWriteResponseChannel).flip
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val ar = Decoupled(new NastiReadAddressChannel)
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val r = Decoupled(new NastiReadDataChannel).flip
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}
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class NastiAddressChannel(implicit p: Parameters) extends NastiMasterToSlaveChannel()(p)
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with HasNastiMetadata
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class NastiResponseChannel(implicit p: Parameters) extends NastiSlaveToMasterChannel()(p) {
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val resp = UInt(width = nastiXRespBits)
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}
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class NastiWriteAddressChannel(implicit p: Parameters) extends NastiAddressChannel()(p) {
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val id = UInt(width = nastiWIdBits)
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val user = UInt(width = nastiAWUserBits)
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}
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class NastiWriteDataChannel(implicit p: Parameters) extends NastiMasterToSlaveChannel()(p)
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with HasNastiData {
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val strb = UInt(width = nastiWStrobeBits)
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val user = UInt(width = nastiWUserBits)
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}
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class NastiWriteResponseChannel(implicit p: Parameters) extends NastiResponseChannel()(p) {
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val id = UInt(width = nastiWIdBits)
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val user = UInt(width = nastiBUserBits)
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}
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class NastiReadAddressChannel(implicit p: Parameters) extends NastiAddressChannel()(p) {
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val id = UInt(width = nastiRIdBits)
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val user = UInt(width = nastiARUserBits)
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}
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class NastiReadDataChannel(implicit p: Parameters) extends NastiResponseChannel()(p)
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with HasNastiData {
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val id = UInt(width = nastiRIdBits)
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val user = UInt(width = nastiRUserBits)
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}
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object NastiWriteAddressChannel {
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def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0))(implicit p: Parameters) = {
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val aw = Wire(new NastiWriteAddressChannel)
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aw.id := id
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aw.addr := addr
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aw.len := len
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aw.size := size
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aw.burst := UInt("b01")
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aw.lock := Bool(false)
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aw.cache := UInt("b0000")
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aw.prot := UInt("b000")
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aw.qos := UInt("b0000")
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aw.region := UInt("b0000")
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aw.user := UInt(0)
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aw
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}
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}
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object NastiReadAddressChannel {
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def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0))(implicit p: Parameters) = {
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val ar = Wire(new NastiReadAddressChannel)
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ar.id := id
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ar.addr := addr
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ar.len := len
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ar.size := size
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ar.burst := UInt("b01")
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ar.lock := Bool(false)
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ar.cache := UInt(0)
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ar.prot := UInt(0)
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ar.qos := UInt(0)
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ar.region := UInt(0)
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ar.user := UInt(0)
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ar
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}
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}
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object NastiWriteDataChannel {
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def apply(data: UInt, last: Bool = Bool(true))(implicit p: Parameters): NastiWriteDataChannel = {
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val w = Wire(new NastiWriteDataChannel)
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w.strb := Fill(w.nastiWStrobeBits, UInt(1, 1))
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w.data := data
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w.last := last
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w.user := UInt(0)
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w
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}
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def apply(data: UInt, strb: UInt, last: Bool)
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(implicit p: Parameters): NastiWriteDataChannel = {
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val w = apply(data, last)
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w.strb := strb
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w
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}
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}
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object NastiReadDataChannel {
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def apply(id: UInt, data: UInt, last: Bool = Bool(true), resp: UInt = UInt(0))(
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implicit p: Parameters) = {
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val r = Wire(new NastiReadDataChannel)
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r.id := id
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r.data := data
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r.last := last
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r.resp := resp
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r.user := UInt(0)
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r
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}
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}
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object NastiWriteResponseChannel {
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def apply(id: UInt, resp: UInt = UInt(0))(implicit p: Parameters) = {
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val b = Wire(new NastiWriteResponseChannel)
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b.id := id
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b.resp := resp
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b.user := UInt(0)
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b
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}
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}
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class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) extends MIFModule
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with HasNastiParameters {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val mem = new MemIO
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}
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require(mifDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree")
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val (mif_cnt_out, mif_wrap_out) = Counter(io.mem.resp.fire(), mifDataBeats)
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.size === UInt(log2Up(mifDataBits/8)),
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"Nasti data size does not match MemIO data size")
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.size === UInt(log2Up(mifDataBits/8)),
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"Nasti data size does not match MemIO data size")
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.len === UInt(mifDataBeats - 1),
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"Nasti length does not match number of MemIO beats")
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.len === UInt(mifDataBeats - 1),
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"Nasti length does not match number of MemIO beats")
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// according to the spec, we can't send b until the last transfer on w
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val b_ok = Reg(init = Bool(true))
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when (io.nasti.aw.fire()) { b_ok := Bool(false) }
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when (io.nasti.w.fire() && io.nasti.w.bits.last) { b_ok := Bool(true) }
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val id_q = Module(new Queue(UInt(width = nastiWIdBits), 2))
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id_q.io.enq.valid := io.nasti.aw.valid && io.mem.req_cmd.ready
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id_q.io.enq.bits := io.nasti.aw.bits.id
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id_q.io.deq.ready := io.nasti.b.ready && b_ok
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io.mem.req_cmd.bits.addr := Mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) >>
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UInt(cacheBlockOffsetBits)
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io.mem.req_cmd.bits.tag := Mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id)
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io.mem.req_cmd.bits.rw := io.nasti.aw.valid
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io.mem.req_cmd.valid := (io.nasti.aw.valid && id_q.io.enq.ready) || io.nasti.ar.valid
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io.nasti.ar.ready := io.mem.req_cmd.ready && !io.nasti.aw.valid
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io.nasti.aw.ready := io.mem.req_cmd.ready && id_q.io.enq.ready
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io.nasti.b.valid := id_q.io.deq.valid && b_ok
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io.nasti.b.bits.id := id_q.io.deq.bits
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io.nasti.b.bits.resp := UInt(0)
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io.nasti.w.ready := io.mem.req_data.ready
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io.mem.req_data.valid := io.nasti.w.valid
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io.mem.req_data.bits.data := io.nasti.w.bits.data
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assert(!io.nasti.w.valid || io.nasti.w.bits.strb.andR, "MemIO must write full cache line")
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io.nasti.r.valid := io.mem.resp.valid
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io.nasti.r.bits.data := io.mem.resp.bits.data
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io.nasti.r.bits.last := mif_wrap_out
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io.nasti.r.bits.id := io.mem.resp.bits.tag
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io.nasti.r.bits.resp := UInt(0)
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io.mem.resp.ready := io.nasti.r.ready
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}
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/** Arbitrate among arbN masters requesting to a single slave */
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class NastiArbiter(val arbN: Int)(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val master = Vec(new NastiIO, arbN).flip
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val slave = new NastiIO
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}
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if (arbN > 1) {
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val arbIdBits = log2Up(arbN)
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val ar_arb = Module(new RRArbiter(new NastiReadAddressChannel, arbN))
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val aw_arb = Module(new RRArbiter(new NastiWriteAddressChannel, arbN))
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val slave_r_arb_id = io.slave.r.bits.id(arbIdBits - 1, 0)
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val slave_b_arb_id = io.slave.b.bits.id(arbIdBits - 1, 0)
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val w_chosen = Reg(UInt(width = arbIdBits))
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val w_done = Reg(init = Bool(true))
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when (aw_arb.io.out.fire()) {
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w_chosen := aw_arb.io.chosen
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w_done := Bool(false)
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}
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when (io.slave.w.fire() && io.slave.w.bits.last) {
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w_done := Bool(true)
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}
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for (i <- 0 until arbN) {
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val m_ar = io.master(i).ar
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val m_aw = io.master(i).aw
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val m_r = io.master(i).r
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val m_b = io.master(i).b
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val a_ar = ar_arb.io.in(i)
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val a_aw = aw_arb.io.in(i)
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val m_w = io.master(i).w
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a_ar <> m_ar
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a_ar.bits.id := Cat(m_ar.bits.id, UInt(i, arbIdBits))
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a_aw <> m_aw
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a_aw.bits.id := Cat(m_aw.bits.id, UInt(i, arbIdBits))
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m_r.valid := io.slave.r.valid && slave_r_arb_id === UInt(i)
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m_r.bits := io.slave.r.bits
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m_r.bits.id := io.slave.r.bits.id >> UInt(arbIdBits)
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m_b.valid := io.slave.b.valid && slave_b_arb_id === UInt(i)
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m_b.bits := io.slave.b.bits
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m_b.bits.id := io.slave.b.bits.id >> UInt(arbIdBits)
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m_w.ready := io.slave.w.ready && w_chosen === UInt(i) && !w_done
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}
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io.slave.r.ready := io.master(slave_r_arb_id).r.ready
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io.slave.b.ready := io.master(slave_b_arb_id).b.ready
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io.slave.w.bits := io.master(w_chosen).w.bits
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io.slave.w.valid := io.master(w_chosen).w.valid && !w_done
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io.slave.ar <> ar_arb.io.out
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io.slave.aw.bits <> aw_arb.io.out.bits
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io.slave.aw.valid := aw_arb.io.out.valid && w_done
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aw_arb.io.out.ready := io.slave.aw.ready && w_done
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} else { io.slave <> io.master.head }
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}
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/** A slave that send decode error for every request it receives */
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class NastiErrorSlave(implicit p: Parameters) extends NastiModule {
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val io = (new NastiIO).flip
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when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
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when (io.aw.fire()) { printf("Invalid write address %x\n", io.aw.bits.addr) }
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val r_queue = Module(new Queue(new NastiReadAddressChannel, 2))
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r_queue.io.enq <> io.ar
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val responding = Reg(init = Bool(false))
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val beats_left = Reg(init = UInt(0, nastiXLenBits))
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when (!responding && r_queue.io.deq.valid) {
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responding := Bool(true)
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beats_left := r_queue.io.deq.bits.len
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}
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io.r.valid := r_queue.io.deq.valid && responding
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io.r.bits.id := r_queue.io.deq.bits.id
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io.r.bits.data := UInt(0)
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io.r.bits.resp := Bits("b11")
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io.r.bits.last := beats_left === UInt(0)
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r_queue.io.deq.ready := io.r.fire() && io.r.bits.last
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when (io.r.fire()) {
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when (beats_left === UInt(0)) {
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responding := Bool(false)
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} .otherwise {
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beats_left := beats_left - UInt(0)
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}
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}
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val draining = Reg(init = Bool(false))
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io.w.ready := draining
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when (io.aw.fire()) { draining := Bool(true) }
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when (io.w.fire() && io.w.bits.last) { draining := Bool(false) }
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val b_queue = Module(new Queue(UInt(width = nastiWIdBits), 2))
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b_queue.io.enq.valid := io.aw.valid && !draining
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b_queue.io.enq.bits := io.aw.bits.id
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io.aw.ready := b_queue.io.enq.ready && !draining
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io.b.valid := b_queue.io.deq.valid && !draining
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io.b.bits.id := b_queue.io.deq.bits
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io.b.bits.resp := Bits("b11")
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b_queue.io.deq.ready := io.b.ready && !draining
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}
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/** Take a single Nasti master and route its requests to various slaves
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* @param nSlaves the number of slaves
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* @param routeSel a function which takes an address and produces
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* a one-hot encoded selection of the slave to write to */
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class NastiRouter(nSlaves: Int, routeSel: UInt => UInt)(implicit p: Parameters)
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extends NastiModule {
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val io = new Bundle {
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val master = (new NastiIO).flip
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val slave = Vec(new NastiIO, nSlaves)
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}
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val ar_route = routeSel(io.master.ar.bits.addr)
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val aw_route = routeSel(io.master.aw.bits.addr)
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var ar_ready = Bool(false)
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var aw_ready = Bool(false)
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var w_ready = Bool(false)
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io.slave.zipWithIndex.foreach { case (s, i) =>
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s.ar.valid := io.master.ar.valid && ar_route(i)
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s.ar.bits := io.master.ar.bits
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ar_ready = ar_ready || (s.ar.ready && ar_route(i))
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s.aw.valid := io.master.aw.valid && aw_route(i)
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s.aw.bits := io.master.aw.bits
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aw_ready = aw_ready || (s.aw.ready && aw_route(i))
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val chosen = Reg(init = Bool(false))
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when (s.aw.fire()) { chosen := Bool(true) }
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when (s.w.fire() && s.w.bits.last) { chosen := Bool(false) }
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s.w.valid := io.master.w.valid && chosen
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s.w.bits := io.master.w.bits
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w_ready = w_ready || (s.w.ready && chosen)
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}
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val r_invalid = !ar_route.orR
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val w_invalid = !aw_route.orR
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val err_slave = Module(new NastiErrorSlave)
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err_slave.io.ar.valid := r_invalid && io.master.ar.valid
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err_slave.io.ar.bits := io.master.ar.bits
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err_slave.io.aw.valid := w_invalid && io.master.aw.valid
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err_slave.io.aw.bits := io.master.aw.bits
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err_slave.io.w.valid := io.master.w.valid
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err_slave.io.w.bits := io.master.w.bits
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io.master.ar.ready := ar_ready || (r_invalid && err_slave.io.ar.ready)
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io.master.aw.ready := aw_ready || (w_invalid && err_slave.io.aw.ready)
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io.master.w.ready := w_ready || err_slave.io.w.ready
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val b_arb = Module(new RRArbiter(new NastiWriteResponseChannel, nSlaves + 1))
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val r_arb = Module(new JunctionsPeekingArbiter(
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new NastiReadDataChannel, nSlaves + 1,
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// we can unlock if it's the last beat
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(r: NastiReadDataChannel) => r.last))
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for (i <- 0 until nSlaves) {
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b_arb.io.in(i) <> io.slave(i).b
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r_arb.io.in(i) <> io.slave(i).r
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}
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b_arb.io.in(nSlaves) <> err_slave.io.b
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r_arb.io.in(nSlaves) <> err_slave.io.r
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io.master.b <> b_arb.io.out
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io.master.r <> r_arb.io.out
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}
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|
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/** Crossbar between multiple Nasti masters and slaves
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* @param nMasters the number of Nasti masters
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* @param nSlaves the number of Nasti slaves
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* @param routeSel a function selecting the slave to route an address to */
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class NastiCrossbar(nMasters: Int, nSlaves: Int, routeSel: UInt => UInt)
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(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val masters = Vec(new NastiIO, nMasters).flip
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val slaves = Vec(new NastiIO, nSlaves)
|
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}
|
|
|
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if (nMasters == 1) {
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val router = Module(new NastiRouter(nSlaves, routeSel))
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router.io.master <> io.masters.head
|
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io.slaves <> router.io.slave
|
|
} else {
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|
val routers = Vec.fill(nMasters) { Module(new NastiRouter(nSlaves, routeSel)).io }
|
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val arbiters = Vec.fill(nSlaves) { Module(new NastiArbiter(nMasters)).io }
|
|
|
|
for (i <- 0 until nMasters) {
|
|
routers(i).master <> io.masters(i)
|
|
}
|
|
|
|
for (i <- 0 until nSlaves) {
|
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arbiters(i).master <> Vec(routers.map(r => r.slave(i)))
|
|
io.slaves(i) <> arbiters(i).slave
|
|
}
|
|
}
|
|
}
|
|
|
|
object NastiMultiChannelRouter {
|
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def apply(master: NastiIO, nChannels: Int)(implicit p: Parameters): Vec[NastiIO] = {
|
|
require(isPow2(nChannels), "Number of channels must be power of 2")
|
|
if (nChannels == 1) {
|
|
Vec(master)
|
|
} else {
|
|
val dataBytes = p(MIFDataBits) * p(MIFDataBeats) / 8
|
|
val selBits = log2Ceil(nChannels)
|
|
val routeSel = (addr: UInt) => {
|
|
Vec.tabulate(nChannels)(i => addr(selBits - 1, 0) === UInt(i)).toBits
|
|
}
|
|
val router = Module(new NastiRouter(nChannels, routeSel))
|
|
router.io.master <> master
|
|
router.io.slave
|
|
}
|
|
}
|
|
}
|
|
|
|
class NastiInterconnectIO(val nMasters: Int, val nSlaves: Int)
|
|
(implicit p: Parameters) extends Bundle {
|
|
/* This is a bit confusing. The interconnect is a slave to the masters and
|
|
* a master to the slaves. Hence why the declarations seem to be backwards. */
|
|
val masters = Vec(new NastiIO, nMasters).flip
|
|
val slaves = Vec(new NastiIO, nSlaves)
|
|
override def cloneType =
|
|
new NastiInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
|
|
}
|
|
|
|
abstract class NastiInterconnect(implicit p: Parameters) extends NastiModule()(p) {
|
|
val nMasters: Int
|
|
val nSlaves: Int
|
|
|
|
lazy val io = new NastiInterconnectIO(nMasters, nSlaves)
|
|
}
|
|
|
|
class NastiRecursiveInterconnect(
|
|
val nMasters: Int,
|
|
val nSlaves: Int,
|
|
addrmap: AddrMap,
|
|
base: BigInt = 0)
|
|
(implicit p: Parameters) extends NastiInterconnect {
|
|
var lastEnd = base
|
|
var slaveInd = 0
|
|
val levelSize = addrmap.size
|
|
val realAddrMap = new ArraySeq[(BigInt, BigInt)](addrmap.size)
|
|
|
|
addrmap.zipWithIndex.foreach { case (AddrMapEntry(_, startOpt, region), i) =>
|
|
val start = startOpt.getOrElse(lastEnd)
|
|
val size = region.size
|
|
realAddrMap(i) = (start, size)
|
|
lastEnd = start + size
|
|
}
|
|
|
|
val routeSel = (addr: UInt) => {
|
|
Vec(realAddrMap.map { case (start, size) =>
|
|
require(bigIntPow2(size),
|
|
s"Region size $size is not a power of 2")
|
|
require(base % size == 0,
|
|
f"Region base address $base%x not divisible by $size%d" )
|
|
|
|
addr >= UInt(start) && addr < UInt(start + size)
|
|
}).toBits
|
|
}
|
|
|
|
val xbar = Module(new NastiCrossbar(nMasters, levelSize, routeSel))
|
|
xbar.io.masters <> io.masters
|
|
|
|
addrmap.zip(realAddrMap).zip(xbar.io.slaves).zipWithIndex.foreach {
|
|
case (((entry, (start, size)), xbarSlave), i) => {
|
|
entry.region match {
|
|
case MemSize(_, _) =>
|
|
io.slaves(slaveInd) <> xbarSlave
|
|
slaveInd += 1
|
|
case MemSubmap(_, submap) =>
|
|
val subSlaves = submap.countSlaves
|
|
val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
|
|
ic.io.masters.head <> xbarSlave
|
|
io.slaves.drop(slaveInd).take(subSlaves).zip(ic.io.slaves).foreach {
|
|
case (s, m) => s <> m
|
|
}
|
|
slaveInd += subSlaves
|
|
case MemChannels(_, nchannels, _) =>
|
|
val routerSlaves = NastiMultiChannelRouter(xbarSlave, nchannels)
|
|
io.slaves.drop(slaveInd).take(nchannels).zip(routerSlaves).foreach {
|
|
case (s, m) => s <> m
|
|
}
|
|
slaveInd += nchannels
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int, addrMap: AddrMap)
|
|
(implicit p: Parameters) extends NastiInterconnect {
|
|
val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap))
|
|
|
|
temp.io.masters.zip(io.masters).foreach { case (t, i) =>
|
|
t.ar <> i.ar
|
|
t.aw <> i.aw
|
|
// this queue is necessary to break up the aw - w dependence
|
|
// introduced by the TileLink -> Nasti converter
|
|
t.w <> Queue(i.w)
|
|
i.b <> t.b
|
|
i.r <> t.r
|
|
}
|
|
//temp.io.masters <> io.masters
|
|
io.slaves <> temp.io.slaves
|
|
}
|