| .. |
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arbiter.scala
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Use HeaderlessTileLinkIO
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2015-04-13 15:58:10 -07:00 |
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btb.scala
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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consts.scala
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Renamed PCR to CSR
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2015-04-11 02:16:44 -07:00 |
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core.scala
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Clean up handling of icache's io.cpu.npc signal
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2015-05-18 18:22:48 -07:00 |
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csr.scala
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New machine-mode timer facility
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2015-07-05 16:38:49 -07:00 |
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ctrl.scala
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
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decode.scala
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fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
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2015-03-10 10:28:05 -07:00 |
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dpath_alu.scala
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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dpath.scala
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Fix an apparently benign PC sign-extension bug
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2015-06-11 16:08:39 -07:00 |
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fpu.scala
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Integrate divide/sqrt unit
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2015-04-04 16:39:17 -07:00 |
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icache.scala
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Use Chisel3 SeqMem construct
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2015-07-11 13:34:57 -07:00 |
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instructions.scala
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New machine-mode timer facility
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2015-07-05 16:38:49 -07:00 |
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multiplier.scala
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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nbdcache.scala
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Use Chisel3 SeqMem construct
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2015-07-11 13:34:57 -07:00 |
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package.scala
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
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ptw.scala
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
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rocc.scala
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HeaderlessTileLinkIO -> ClientTileLinkIO
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2015-04-17 16:56:53 -07:00 |
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tile.scala
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HeaderlessTileLinkIO -> ClientTileLinkIO
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2015-04-17 16:56:53 -07:00 |
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tlb.scala
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Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
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util.scala
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
