121 lines
3.7 KiB
Scala
121 lines
3.7 KiB
Scala
package uncore
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import Chisel._
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import Constants._
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class PhysicalAddress extends Bundle {
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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}
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class MemReqCmd extends PhysicalAddress {
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val rw = Bool()
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val tag = Bits(width = MEM_TAG_BITS)
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}
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class MemResp extends MemData {
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val tag = Bits(width = MEM_TAG_BITS)
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}
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class ioMem extends Bundle {
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val req_cmd = (new FIFOIO) { new MemReqCmd() }
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val req_data = (new FIFOIO) { new MemData() }
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val resp = (new FIFOIO) { new MemResp() }.flip
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}
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class ioMemPipe extends Bundle {
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val req_cmd = (new FIFOIO) { new MemReqCmd() }
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val req_data = (new FIFOIO) { new MemData() }
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val resp = (new PipeIO) { new MemResp() }.flip
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}
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class Acquire extends PhysicalAddress {
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val a_type = Bits(width = ACQUIRE_TYPE_MAX_BITS)
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val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
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val write_mask = Bits(width = ACQUIRE_WRITE_MASK_BITS)
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val subword_addr = Bits(width = ACQUIRE_SUBWORD_ADDR_BITS)
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val atomic_opcode = Bits(width = ACQUIRE_ATOMIC_OP_BITS)
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}
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object Acquire
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{
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def apply(a_type: Bits, addr: UFix, client_xact_id: UFix) = {
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val acq = new Acquire
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acq.a_type := a_type
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acq.addr := addr
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acq.client_xact_id := client_xact_id
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acq
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}
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def apply(a_type: Bits, addr: UFix, client_xact_id: UFix, write_mask: Bits) = {
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val acq = new Acquire
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acq.a_type := a_type
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acq.addr := addr
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acq.client_xact_id := client_xact_id
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acq.write_mask := write_mask
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acq
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}
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def apply(a_type: Bits, addr: UFix, client_xact_id: UFix, subword_addr: UFix, atomic_opcode: UFix) = {
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val acq = new Acquire
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acq.a_type := a_type
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acq.addr := addr
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acq.client_xact_id := client_xact_id
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acq.subword_addr := subword_addr
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acq.atomic_opcode := atomic_opcode
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acq
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}
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}
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class AcquireData extends MemData
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class Probe extends PhysicalAddress {
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val p_type = Bits(width = PROBE_TYPE_MAX_BITS)
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val master_xact_id = Bits(width = MASTER_XACT_ID_BITS)
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}
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object Release
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{
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def apply(r_type: Bits, addr: UFix, client_xact_id: UFix, master_xact_id: UFix) = {
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val rel = new Release
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rel.r_type := r_type
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rel.addr := addr
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rel.client_xact_id := client_xact_id
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rel.master_xact_id := master_xact_id
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rel
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}
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}
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class Release extends PhysicalAddress {
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val r_type = Bits(width = RELEASE_TYPE_MAX_BITS)
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val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
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val master_xact_id = Bits(width = MASTER_XACT_ID_BITS)
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}
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class ReleaseData extends MemData
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class Grant extends MemData {
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val g_type = Bits(width = GRANT_TYPE_MAX_BITS)
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val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
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val master_xact_id = Bits(width = MASTER_XACT_ID_BITS)
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}
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class GrantAck extends Bundle {
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val master_xact_id = Bits(width = MASTER_XACT_ID_BITS)
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}
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abstract class DirectionalFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data)
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class ClientSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data)
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class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) {flip()}
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class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }}
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val acquire_data = (new ClientSourcedIO){(new LogicalNetworkIO){new AcquireData }}
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val probe = (new MasterSourcedIO){(new LogicalNetworkIO){new Probe }}
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val release = (new ClientSourcedIO){(new LogicalNetworkIO){new Release }}
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val release_data = (new ClientSourcedIO){(new LogicalNetworkIO){new ReleaseData }}
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val grant = (new MasterSourcedIO){(new LogicalNetworkIO){new Grant }}
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val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }}
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override def clone = { new TileLinkIO().asInstanceOf[this.type] }
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}
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