rocket-chip

riscv

History

Henry Cook 01ca3efc2b Combine Coreplex and System Module Hierarchies (#875 ) * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless := and := * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC	2017-07-23 08:31:04 -07:00
..
.gitignore	Add torture as part of the regression	2016-01-31 23:06:59 -08:00
Makefile	Combine Coreplex and System Module Hierarchies (#875 )	2017-07-23 08:31:04 -07:00

Henry Cook 01ca3efc2b Combine Coreplex and System Module Hierarchies (#875 )

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

2017-07-23 08:31:04 -07:00

.gitignore

Add torture as part of the regression

2016-01-31 23:06:59 -08:00

Makefile

Combine Coreplex and System Module Hierarchies (#875 )

2017-07-23 08:31:04 -07:00