105 lines
3.2 KiB
Scala
105 lines
3.2 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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case object LNEndpoints extends Field[Int]
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case object LNHeaderBits extends Field[Int]
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class PhysicalHeader(n: Int) extends Bundle {
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val src = UInt(width = log2Up(n))
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val dst = UInt(width = log2Up(n))
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}
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class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle {
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val header = new PhysicalHeader(n)
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val payload = dType
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override def cloneType = new PhysicalNetworkIO(n,dType).asInstanceOf[this.type]
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}
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class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
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val in = Vec.fill(n){Decoupled(new PhysicalNetworkIO(n,dType))}.flip
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val out = Vec.fill(n){Decoupled(new PhysicalNetworkIO(n,dType))}
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}
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abstract class PhysicalNetwork extends Module
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class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork {
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val io = new BasicCrossbarIO(n, dType)
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val rdyVecs = List.fill(n){Vec.fill(n)(Bool())}
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock))
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(rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
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arb.valid := in.valid && (in.bits.header.dst === UInt(i))
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arb.bits := in.bits
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rdy := arb.ready && (in.bits.header.dst === UInt(i))
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}}
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out <> rrarb.io.out
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}}
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for(i <- 0 until n) {
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io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
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}
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}
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abstract class LogicalNetwork extends Module
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class LogicalHeader extends Bundle {
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val src = UInt(width = params(LNHeaderBits))
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val dst = UInt(width = params(LNHeaderBits))
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}
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class LogicalNetworkIO[T <: Data](dType: T) extends Bundle {
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val header = new LogicalHeader
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val payload = dType.cloneType
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override def cloneType = new LogicalNetworkIO(dType).asInstanceOf[this.type]
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}
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object DecoupledLogicalNetworkIOWrapper {
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def apply[T <: Data](
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in: DecoupledIO[T],
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src: UInt = UInt(0),
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dst: UInt = UInt(0)): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = Decoupled(new LogicalNetworkIO(in.bits)).asDirectionless
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out.valid := in.valid
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out.bits.payload := in.bits
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out.bits.header.dst := dst
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out.bits.header.src := src
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in.ready := out.ready
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out
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}
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}
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object DecoupledLogicalNetworkIOUnwrapper {
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def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[T] = {
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val out = Decoupled(in.bits.payload).asDirectionless
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out.valid := in.valid
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out.bits := in.bits.payload
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in.ready := out.ready
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out
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}
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}
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object DefaultFromPhysicalShim {
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def apply[T <: Data](in: DecoupledIO[PhysicalNetworkIO[T]]): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = Decoupled(new LogicalNetworkIO(in.bits.payload)).asDirectionless
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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object DefaultToPhysicalShim {
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def apply[T <: Data](n: Int, in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[PhysicalNetworkIO[T]] = {
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val out = Decoupled(new PhysicalNetworkIO(n, in.bits.payload)).asDirectionless
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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