184 lines
4.2 KiB
Verilog
184 lines
4.2 KiB
Verilog
// See LICENSE for license details.
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extern "A" void debug_tick
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(
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output reg debug_req_valid,
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input reg debug_req_ready,
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output reg [ 4:0] debug_req_bits_addr,
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output reg [ 1:0] debug_req_bits_op,
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output reg [33:0] debug_req_bits_data,
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input reg debug_resp_valid,
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output reg debug_resp_ready,
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input reg [ 1:0] debug_resp_bits_resp,
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input reg [33:0] debug_resp_bits_data,
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output reg [31:0] exit
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);
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extern "A" void memory_tick
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(
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input reg [31:0] channel,
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input reg ar_valid,
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output reg ar_ready,
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input reg [`MEM_ADDR_BITS-1:0] ar_addr,
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input reg [`MEM_ID_BITS-1:0] ar_id,
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input reg [2:0] ar_size,
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input reg [7:0] ar_len,
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input reg aw_valid,
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output reg aw_ready,
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input reg [`MEM_ADDR_BITS-1:0] aw_addr,
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input reg [`MEM_ID_BITS-1:0] aw_id,
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input reg [2:0] aw_size,
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input reg [7:0] aw_len,
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input reg w_valid,
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output reg w_ready,
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input reg [`MEM_STRB_BITS-1:0] w_strb,
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input reg [`MEM_DATA_BITS-1:0] w_data,
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input reg w_last,
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output reg r_valid,
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input reg r_ready,
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output reg [1:0] r_resp,
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output reg [`MEM_ID_BITS-1:0] r_id,
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output reg [`MEM_DATA_BITS-1:0] r_data,
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output reg r_last,
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output reg b_valid,
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input reg b_ready,
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output reg [1:0] b_resp,
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output reg [`MEM_ID_BITS-1:0] b_id
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);
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module rocketTestHarness;
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reg [31:0] seed;
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initial seed = $get_initial_random_seed();
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//-----------------------------------------------
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// Instantiate the processor
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reg clk = 1'b0;
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reg reset = 1'b1;
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reg r_reset = 1'b1;
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reg start = 1'b0;
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always #`CLOCK_PERIOD clk = ~clk;
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reg [ 31:0] n_mem_channel = `N_MEM_CHANNELS;
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reg [ 31:0] mem_width = `MEM_DATA_BITS;
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reg [ 63:0] max_cycles = 0;
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reg [ 63:0] trace_count = 0;
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reg [1023:0] loadmem = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [1023:0] vcdfile = 0;
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reg verbose = 0;
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wire printf_cond = verbose && !reset;
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integer stderr = 32'h80000002;
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`include `TBVFRAG
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always @(posedge clk)
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begin
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r_reset <= reset;
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end
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reg [31:0] exit = 0;
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always @(posedge clk)
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begin
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if (reset || r_reset)
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begin
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debug_req_valid <= 0;
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debug_resp_ready <= 0;
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end
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else
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begin
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debug_tick
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(
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debug_req_valid,
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debug_req_ready,
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debug_req_bits_addr,
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debug_req_bits_op,
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debug_req_bits_data,
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debug_resp_valid,
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debug_resp_ready,
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debug_resp_bits_resp,
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debug_resp_bits_data,
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exit
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);
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end
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end
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//-----------------------------------------------
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// Start the simulation
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// Read input arguments and initialize
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initial
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begin
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$value$plusargs("max-cycles=%d", max_cycles);
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verbose = $test$plusargs("verbose");
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`ifdef DEBUG
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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$vcdplusfile(vcdplusfile);
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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if ($value$plusargs("vcdfile=%s", vcdfile))
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begin
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$dumpfile(vcdfile);
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$dumpvars(0, dut);
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$dumpon;
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end
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`else
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`define VCDPLUSCLOSE
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`endif
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// Strobe reset
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#777.7 reset = 0;
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end
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reg [255:0] reason = 0;
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always @(posedge clk)
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begin
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if (max_cycles > 0 && trace_count > max_cycles)
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reason = "timeout";
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if (exit > 1)
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$sformat(reason, "tohost = %d", exit >> 1);
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if (reason)
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begin
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$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
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`VCDPLUSCLOSE
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$fatal;
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end
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if (exit == 1)
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begin
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if (verbose)
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$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
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`VCDPLUSCLOSE
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$finish;
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end
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end
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always @(posedge clk)
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begin
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trace_count = trace_count + 1;
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`ifdef GATE_LEVEL
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if (verbose)
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begin
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$fdisplay(stderr, "C: %10d", trace_count-1);
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end
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`endif
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end
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endmodule
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