401 lines
13 KiB
Scala
401 lines
13 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.Parameters
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import uncore.devices.{DbBusConsts, DMKey}
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import coreplex._
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object TestBenchGeneration {
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def generateVerilogFragment(
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topModuleName: String, configClassName: String, p: Parameters) = {
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val nMemChannel = p(NMemoryChannels)
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// YUNSUP:
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// I originally wrote this using a 2d wire array, but of course Synopsys'
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// DirectC implementation totally chokes on it when the 2d array is
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// referenced by the first dimension: the wire shows up as a contiguous
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// bit collection on the DirectC side. I had to individually define the
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// wires.
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val daw = p(DMKey).nDebugBusAddrSize
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val dow = DbBusConsts.dbOpSize
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val ddw = DbBusConsts.dbDataSize
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val drw = DbBusConsts.dbRespSize
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val debugDefs = s"""
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wire debug_req_valid_delay;
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reg debug_req_valid;
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assign #0.1 debug_req_valid_delay = debug_req_valid;
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wire debug_req_ready, debug_req_ready_delay;
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assign #0.1 debug_req_ready = debug_req_ready_delay;
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wire [${daw-1}:0] debug_req_bits_addr_delay;
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reg [${daw-1}:0] debug_req_bits_addr;
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assign #0.1 debug_req_bits_addr_delay = debug_req_bits_addr;
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wire [${dow-1}:0] debug_req_bits_op_delay;
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reg [${dow-1}:0] debug_req_bits_op;
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assign #0.1 debug_req_bits_op_delay = debug_req_bits_op;
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wire [${ddw-1}:0] debug_req_bits_data_delay;
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reg [${ddw-1}:0] debug_req_bits_data;
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assign #0.1 debug_req_bits_data_delay = debug_req_bits_data;
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wire debug_resp_valid, debug_resp_valid_delay;
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assign #0.1 debug_resp_valid = debug_resp_valid_delay;
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wire debug_resp_ready_delay;
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reg debug_resp_ready;
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assign #0.1 debug_resp_ready_delay = debug_resp_ready;
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wire [${drw-1}:0] debug_resp_bits_resp, debug_resp_bits_resp_delay;
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assign #0.1 debug_resp_bits_resp = debug_resp_bits_resp_delay;
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wire [${ddw-1}:0] debug_resp_bits_data, debug_resp_bits_data_delay;
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assign #0.1 debug_resp_bits_data = debug_resp_bits_data_delay;
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"""
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val debugBus = s"""
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.io_debug_req_ready(debug_req_ready_delay),
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.io_debug_req_valid(debug_req_valid_delay),
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.io_debug_req_bits_addr(debug_req_bits_addr_delay),
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.io_debug_req_bits_op(debug_req_bits_op_delay),
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.io_debug_req_bits_data(debug_req_bits_data_delay),
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.io_debug_resp_ready(debug_resp_ready_delay),
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.io_debug_resp_valid(debug_resp_valid_delay),
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.io_debug_resp_bits_resp(debug_resp_bits_resp_delay),
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.io_debug_resp_bits_data(debug_resp_bits_data_delay)
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"""
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val nasti_defs = (0 until nMemChannel) map { i => s"""
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wire ar_valid_$i;
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reg ar_ready_$i;
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wire [`MEM_ADDR_BITS-1:0] ar_addr_$i;
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wire [`MEM_ID_BITS-1:0] ar_id_$i;
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wire [2:0] ar_size_$i;
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wire [7:0] ar_len_$i;
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wire aw_valid_$i;
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reg aw_ready_$i;
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wire [`MEM_ADDR_BITS-1:0] aw_addr_$i;
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wire [`MEM_ID_BITS-1:0] aw_id_$i;
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wire [2:0] aw_size_$i;
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wire [7:0] aw_len_$i;
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wire w_valid_$i;
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reg w_ready_$i;
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wire [`MEM_STRB_BITS-1:0] w_strb_$i;
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wire [`MEM_DATA_BITS-1:0] w_data_$i;
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wire w_last_$i;
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reg r_valid_$i;
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wire r_ready_$i;
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reg [1:0] r_resp_$i;
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reg [`MEM_ID_BITS-1:0] r_id_$i;
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reg [`MEM_DATA_BITS-1:0] r_data_$i;
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reg r_last_$i;
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reg b_valid_$i;
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wire b_ready_$i;
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reg [1:0] b_resp_$i;
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reg [`MEM_ID_BITS-1:0] b_id_$i;
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""" } mkString
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val nasti_delays = (0 until nMemChannel) map { i => s"""
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wire ar_valid_delay_$i;
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wire ar_ready_delay_$i;
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wire [`MEM_ADDR_BITS-1:0] ar_addr_delay_$i;
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wire [`MEM_ID_BITS-1:0] ar_id_delay_$i;
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wire [2:0] ar_size_delay_$i;
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wire [7:0] ar_len_delay_$i;
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wire aw_valid_delay_$i;
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wire aw_ready_delay_$i;
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wire [`MEM_ADDR_BITS-1:0] aw_addr_delay_$i;
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wire [`MEM_ID_BITS-1:0] aw_id_delay_$i;
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wire [2:0] aw_size_delay_$i;
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wire [7:0] aw_len_delay_$i;
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wire w_valid_delay_$i;
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wire w_ready_delay_$i;
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wire [`MEM_STRB_BITS-1:0] w_strb_delay_$i;
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wire [`MEM_DATA_BITS-1:0] w_data_delay_$i;
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wire w_last_delay_$i;
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wire r_valid_delay_$i;
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wire r_ready_delay_$i;
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wire [1:0] r_resp_delay_$i;
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wire [`MEM_ID_BITS-1:0] r_id_delay_$i;
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wire [`MEM_DATA_BITS-1:0] r_data_delay_$i;
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wire r_last_delay_$i;
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wire b_valid_delay_$i;
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wire b_ready_delay_$i;
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wire [1:0] b_resp_delay_$i;
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wire [`MEM_ID_BITS-1:0] b_id_delay_$i;
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assign #0.1 ar_valid_$i = ar_valid_delay_$i;
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assign #0.1 ar_ready_delay_$i = ar_ready_$i;
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assign #0.1 ar_addr_$i = ar_addr_delay_$i;
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assign #0.1 ar_id_$i = ar_id_delay_$i;
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assign #0.1 ar_size_$i = ar_size_delay_$i;
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assign #0.1 ar_len_$i = ar_len_delay_$i;
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assign #0.1 aw_valid_$i = aw_valid_delay_$i;
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assign #0.1 aw_ready_delay_$i = aw_ready_$i;
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assign #0.1 aw_addr_$i = aw_addr_delay_$i;
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assign #0.1 aw_id_$i = aw_id_delay_$i;
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assign #0.1 aw_size_$i = aw_size_delay_$i;
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assign #0.1 aw_len_$i = aw_len_delay_$i;
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assign #0.1 w_valid_$i = w_valid_delay_$i;
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assign #0.1 w_ready_delay_$i = w_ready_$i;
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assign #0.1 w_strb_$i = w_strb_delay_$i;
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assign #0.1 w_data_$i = w_data_delay_$i;
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assign #0.1 w_last_$i = w_last_delay_$i;
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assign #0.1 r_valid_delay_$i = r_valid_$i;
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assign #0.1 r_ready_$i = r_ready_delay_$i;
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assign #0.1 r_resp_delay_$i = r_resp_$i;
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assign #0.1 r_id_delay_$i = r_id_$i;
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assign #0.1 r_data_delay_$i = r_data_$i;
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assign #0.1 r_last_delay_$i = r_last_$i;
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assign #0.1 b_valid_delay_$i = b_valid_$i;
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assign #0.1 b_ready_$i = b_ready_delay_$i;
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assign #0.1 b_resp_delay_$i = b_resp_$i;
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assign #0.1 b_id_delay_$i = b_id_$i;
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""" } mkString
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val nasti_connections = (0 until nMemChannel) map { i => s"""
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.io_mem_axi_${i}_ar_valid (ar_valid_delay_$i),
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.io_mem_axi_${i}_ar_ready (ar_ready_delay_$i),
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.io_mem_axi_${i}_ar_bits_addr (ar_addr_delay_$i),
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.io_mem_axi_${i}_ar_bits_id (ar_id_delay_$i),
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.io_mem_axi_${i}_ar_bits_size (ar_size_delay_$i),
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.io_mem_axi_${i}_ar_bits_len (ar_len_delay_$i),
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.io_mem_axi_${i}_ar_bits_burst (),
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.io_mem_axi_${i}_ar_bits_lock (),
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.io_mem_axi_${i}_ar_bits_cache (),
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.io_mem_axi_${i}_ar_bits_prot (),
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.io_mem_axi_${i}_ar_bits_qos (),
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.io_mem_axi_${i}_ar_bits_region (),
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.io_mem_axi_${i}_ar_bits_user (),
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.io_mem_axi_${i}_aw_valid (aw_valid_delay_$i),
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.io_mem_axi_${i}_aw_ready (aw_ready_delay_$i),
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.io_mem_axi_${i}_aw_bits_addr (aw_addr_delay_$i),
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.io_mem_axi_${i}_aw_bits_id (aw_id_delay_$i),
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.io_mem_axi_${i}_aw_bits_size (aw_size_delay_$i),
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.io_mem_axi_${i}_aw_bits_len (aw_len_delay_$i),
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.io_mem_axi_${i}_aw_bits_burst (),
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.io_mem_axi_${i}_aw_bits_lock (),
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.io_mem_axi_${i}_aw_bits_cache (),
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.io_mem_axi_${i}_aw_bits_prot (),
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.io_mem_axi_${i}_aw_bits_qos (),
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.io_mem_axi_${i}_aw_bits_region (),
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.io_mem_axi_${i}_aw_bits_user (),
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.io_mem_axi_${i}_w_valid (w_valid_delay_$i),
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.io_mem_axi_${i}_w_ready (w_ready_delay_$i),
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.io_mem_axi_${i}_w_bits_id (),
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.io_mem_axi_${i}_w_bits_strb (w_strb_delay_$i),
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.io_mem_axi_${i}_w_bits_data (w_data_delay_$i),
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.io_mem_axi_${i}_w_bits_last (w_last_delay_$i),
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.io_mem_axi_${i}_w_bits_user (),
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.io_mem_axi_${i}_r_valid (r_valid_delay_$i),
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.io_mem_axi_${i}_r_ready (r_ready_delay_$i),
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.io_mem_axi_${i}_r_bits_resp (r_resp_delay_$i),
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.io_mem_axi_${i}_r_bits_id (r_id_delay_$i),
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.io_mem_axi_${i}_r_bits_data (r_data_delay_$i),
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.io_mem_axi_${i}_r_bits_last (r_last_delay_$i),
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.io_mem_axi_${i}_r_bits_user (1'b0),
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.io_mem_axi_${i}_b_valid (b_valid_delay_$i),
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.io_mem_axi_${i}_b_ready (b_ready_delay_$i),
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.io_mem_axi_${i}_b_bits_resp (b_resp_delay_$i),
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.io_mem_axi_${i}_b_bits_id (b_id_delay_$i),
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.io_mem_axi_${i}_b_bits_user (1'b0),
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""" } mkString
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val interrupts = (0 until p(NExtInterrupts)) map { i => s"""
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.io_interrupts_$i (1'b0),
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""" } mkString
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val instantiation = s"""
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${topModuleName} dut
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(
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.clk(clk),
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.reset(reset),
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$nasti_connections
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$interrupts
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$debugBus
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);
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"""
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val ticks = (0 until nMemChannel) map { i => s"""
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reg [31:0] channel_$i = $i;
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always @(posedge clk)
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begin
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if (reset || r_reset)
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begin
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ar_ready_$i <= 1'b0;
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aw_ready_$i <= 1'b0;
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w_ready_$i <= 1'b0;
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r_valid_$i <= 1'b0;
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r_resp_$i <= 2'b0;
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r_id_$i <= {`MEM_ID_BITS {1'b0}};
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r_data_$i <= {`MEM_DATA_BITS {1'b0}};
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r_last_$i <= 1'b0;
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b_valid_$i <= 1'b0;
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b_resp_$i <= 2'b0;
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b_id_$i <= {`MEM_ID_BITS {1'b0}};
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end
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else
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begin
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memory_tick
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(
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channel_$i,
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ar_valid_$i, ar_ready_$i, ar_addr_$i, ar_id_$i, ar_size_$i, ar_len_$i,
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aw_valid_$i, aw_ready_$i, aw_addr_$i, aw_id_$i, aw_size_$i, aw_len_$i,
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w_valid_$i, w_ready_$i, w_strb_$i, w_data_$i, w_last_$i,
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r_valid_$i, r_ready_$i, r_resp_$i, r_id_$i, r_data_$i, r_last_$i,
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b_valid_$i, b_ready_$i, b_resp_$i, b_id_$i
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);
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end
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end
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always @(posedge clk)
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begin
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if (verbose)
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begin
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if (ar_valid_$i && ar_ready_$i)
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begin
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$$fdisplay(stderr, "MC$i: ar addr=%x size=%x", ar_addr_$i, ar_size_$i);
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end
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if (aw_valid_$i && aw_ready_$i)
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begin
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$$fdisplay(stderr, "MC$i: aw addr=%x size=%x", aw_addr_$i, aw_size_$i);
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end
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if (w_valid_$i && w_ready_$i)
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begin
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$$fdisplay(stderr, "MC$i: w data=%x strb=%x", w_data_$i, w_strb_$i);
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end
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if (r_valid_$i && r_ready_$i)
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begin
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$$fdisplay(stderr, "MC$i: r data=%x", r_data_$i);
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end
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end
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end
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""" } mkString
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val f = TestGeneration.createOutputFile(s"$topModuleName.$configClassName.tb.vfrag")
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f.write(debugDefs + nasti_defs + nasti_delays + instantiation + ticks)
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f.close
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}
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def generateCPPFragment(
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topModuleName: String, configClassName: String, p: Parameters) = {
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val nMemChannel = p(NMemoryChannels)
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val assigns = (0 until nMemChannel).map { i => s"""
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#ifndef VERILATOR
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mem_ar_valid[$i] = &tile.Top__io_mem_axi_${i}_ar_valid;
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mem_ar_ready[$i] = &tile.Top__io_mem_axi_${i}_ar_ready;
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mem_ar_bits_addr[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_addr;
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mem_ar_bits_id[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_id;
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mem_ar_bits_size[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_size;
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mem_ar_bits_len[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_len;
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mem_aw_valid[$i] = &tile.Top__io_mem_axi_${i}_aw_valid;
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mem_aw_ready[$i] = &tile.Top__io_mem_axi_${i}_aw_ready;
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mem_aw_bits_addr[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_addr;
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mem_aw_bits_id[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_id;
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mem_aw_bits_size[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_size;
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mem_aw_bits_len[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_len;
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mem_w_valid[$i] = &tile.Top__io_mem_axi_${i}_w_valid;
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mem_w_ready[$i] = &tile.Top__io_mem_axi_${i}_w_ready;
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mem_w_bits_data[$i] = &tile.Top__io_mem_axi_${i}_w_bits_data;
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mem_w_bits_strb[$i] = &tile.Top__io_mem_axi_${i}_w_bits_strb;
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mem_w_bits_last[$i] = &tile.Top__io_mem_axi_${i}_w_bits_last;
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mem_b_valid[$i] = &tile.Top__io_mem_axi_${i}_b_valid;
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mem_b_ready[$i] = &tile.Top__io_mem_axi_${i}_b_ready;
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mem_b_bits_resp[$i] = &tile.Top__io_mem_axi_${i}_b_bits_resp;
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mem_b_bits_id[$i] = &tile.Top__io_mem_axi_${i}_b_bits_id;
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mem_r_valid[$i] = &tile.Top__io_mem_axi_${i}_r_valid;
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mem_r_ready[$i] = &tile.Top__io_mem_axi_${i}_r_ready;
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mem_r_bits_resp[$i] = &tile.Top__io_mem_axi_${i}_r_bits_resp;
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mem_r_bits_id[$i] = &tile.Top__io_mem_axi_${i}_r_bits_id;
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mem_r_bits_data[$i] = &tile.Top__io_mem_axi_${i}_r_bits_data;
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mem_r_bits_last[$i] = &tile.Top__io_mem_axi_${i}_r_bits_last;
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#else
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mem_ar_valid[$i] = &tile.io_mem_axi_${i}_ar_valid;
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mem_ar_ready[$i] = &tile.io_mem_axi_${i}_ar_ready;
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mem_ar_bits_addr[$i] = &tile.io_mem_axi_${i}_ar_bits_addr;
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mem_ar_bits_id[$i] = &tile.io_mem_axi_${i}_ar_bits_id;
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mem_ar_bits_size[$i] = &tile.io_mem_axi_${i}_ar_bits_size;
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mem_ar_bits_len[$i] = &tile.io_mem_axi_${i}_ar_bits_len;
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mem_aw_valid[$i] = &tile.io_mem_axi_${i}_aw_valid;
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mem_aw_ready[$i] = &tile.io_mem_axi_${i}_aw_ready;
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mem_aw_bits_addr[$i] = &tile.io_mem_axi_${i}_aw_bits_addr;
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mem_aw_bits_id[$i] = &tile.io_mem_axi_${i}_aw_bits_id;
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mem_aw_bits_size[$i] = &tile.io_mem_axi_${i}_aw_bits_size;
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mem_aw_bits_len[$i] = &tile.io_mem_axi_${i}_aw_bits_len;
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mem_w_valid[$i] = &tile.io_mem_axi_${i}_w_valid;
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mem_w_ready[$i] = &tile.io_mem_axi_${i}_w_ready;
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#if MEM_DATA_BITS > 64
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mem_w_bits_data[$i] = tile.io_mem_axi_${i}_w_bits_data;
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#else
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mem_w_bits_data[$i] = &tile.io_mem_axi_${i}_w_bits_data;
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#endif
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mem_w_bits_strb[$i] = &tile.io_mem_axi_${i}_w_bits_strb;
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mem_w_bits_last[$i] = &tile.io_mem_axi_${i}_w_bits_last;
|
|
|
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mem_b_valid[$i] = &tile.io_mem_axi_${i}_b_valid;
|
|
mem_b_ready[$i] = &tile.io_mem_axi_${i}_b_ready;
|
|
mem_b_bits_resp[$i] = &tile.io_mem_axi_${i}_b_bits_resp;
|
|
mem_b_bits_id[$i] = &tile.io_mem_axi_${i}_b_bits_id;
|
|
|
|
mem_r_valid[$i] = &tile.io_mem_axi_${i}_r_valid;
|
|
mem_r_ready[$i] = &tile.io_mem_axi_${i}_r_ready;
|
|
mem_r_bits_resp[$i] = &tile.io_mem_axi_${i}_r_bits_resp;
|
|
mem_r_bits_id[$i] = &tile.io_mem_axi_${i}_r_bits_id;
|
|
#if MEM_DATA_BITS > 64
|
|
mem_r_bits_data[$i] = tile.io_mem_axi_${i}_r_bits_data;
|
|
#else
|
|
mem_r_bits_data[$i] = &tile.io_mem_axi_${i}_r_bits_data;
|
|
#endif
|
|
mem_r_bits_last[$i] = &tile.io_mem_axi_${i}_r_bits_last;
|
|
#endif
|
|
""" }.mkString
|
|
|
|
val interrupts = (0 until p(NExtInterrupts)) map { i => s"""
|
|
#ifndef VERILATOR
|
|
tile.Top__io_interrupts_$i = LIT<1>(0);
|
|
#else
|
|
tile.io_interrupts_$i = 0;
|
|
#endif
|
|
""" } mkString
|
|
|
|
val f = TestGeneration.createOutputFile(s"$topModuleName.$configClassName.tb.cpp")
|
|
f.write(assigns)
|
|
f.write(interrupts)
|
|
f.close
|
|
}
|
|
}
|