a031686763
* util: Do Set/Reset Async Registers more properly The way BlackBox "init" registers were coded before was not really kosher verilog for most synthesis tools. Also, the enable logic wasn't really pushed down into the flop. This change is more explicit about set/reset flops, again this is only a 'temporary' problem that would go away with parameterizable blackboxes (or general async reset support). * Tabs, not spaces, in Makefiles * util: Fix typos in Async BB Reg Comments
48 lines
978 B
Verilog
48 lines
978 B
Verilog
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/** This black-boxes an Async Set
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* Reg.
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*
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* Because Chisel doesn't support
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* parameterized black boxes,
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* we unfortunately have to
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* instantiate a number of these.
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*
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* We also have to hard-code the set/reset.
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*
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* Do not confuse an asynchronous
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* reset signal with an asynchronously
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* reset reg. You should still
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* properly synchronize your reset
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* deassertion.
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*
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* @param d Data input
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* @param q Data Output
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* @param clk Clock Input
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* @param rst Reset Input
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* @param en Write Enable Input
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*
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*/
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module AsyncSetReg (
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input d,
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output reg q,
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input en,
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input clk,
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input rst);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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q <= 1'b1;
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end else if (en) begin
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q <= d;
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end
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end
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endmodule // AsyncSetReg
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