69 lines
2.1 KiB
Scala
69 lines
2.1 KiB
Scala
package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import groundtest._
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import groundtest.common._
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import uncore.tilelink._
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import uncore.agents._
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case object ExportGroundTestStatus extends Field[Boolean]
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class DirectGroundTestTop(topParams: Parameters) extends Module
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with HasTopLevelParameters {
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implicit val p = topParams
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val io = new TopIO {
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// Need to export this for FPGA testing, but not for simulator
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val status = if (p(ExportGroundTestStatus)) Some(new GroundTestStatus) else None
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}
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// Not using the debug
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io.debug.req.ready := Bool(false)
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io.debug.resp.valid := Bool(false)
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require(io.mmio_axi.isEmpty && io.mmio_ahb.isEmpty && io.mmio_tl.isEmpty)
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require(io.mem_ahb.isEmpty && io.mem_tl.isEmpty)
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require(nMemChannels == 1)
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require(nTiles == 1)
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val test = p(BuildGroundTest)(outermostParams.alterPartial({
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case GroundTestId => 0
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case CacheName => "L1D"
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}))
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require(test.io.cache.size == 0)
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require(test.io.mem.size == nBanksPerMemChannel)
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require(test.io.ptw.size == 0)
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when (test.io.status.finished) { stop() }
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val mem_ic = Module(new TileLinkMemoryInterconnect(
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nBanksPerMemChannel, nMemChannels)(outermostParams))
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mem_ic.io.in <> test.io.mem
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io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) =>
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TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
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}
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io.status.map { status =>
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val s_running :: s_finished :: s_errored :: s_timeout :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_running)
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val error_code = Reg(status.error.bits)
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val timeout_code = Reg(status.timeout.bits)
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when (state === s_running) {
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when (test.io.status.finished) { state := s_finished }
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when (test.io.status.error.valid) {
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state := s_errored
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error_code := test.io.status.error.bits
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}
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when (test.io.status.timeout.valid) {
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state := s_timeout
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timeout_code := test.io.status.timeout.bits
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}
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}
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status.finished := (state === s_finished)
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status.error.valid := (state === s_errored)
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status.error.bits := error_code
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status.timeout.valid := (state === s_timeout)
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status.timeout.bits := timeout_code
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}
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}
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