260 lines
9.6 KiB
Scala
260 lines
9.6 KiB
Scala
package rocket
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import Chisel._
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import Constants._
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class TransactionInit extends Bundle {
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val t_type = Bits(width = X_INIT_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = UFix(width = PADDR_BITS - OFFSET_BITS)
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}
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class TransactionInitData extends MemData
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class TransactionAbort extends Bundle {
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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}
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class ProbeRequest extends Bundle {
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val p_type = Bits(width = P_REQ_TYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS - OFFSET_BITS)
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}
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class ProbeReply extends Bundle {
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val p_type = Bits(width = P_REP_TYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends MemData
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class TransactionReply extends MemData {
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val t_type = Bits(width = X_REP_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val require_ack = Bool()
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}
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class TransactionFinish extends Bundle {
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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object cpuCmdToRW {
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def apply(cmd: Bits): (Bool, Bool) = {
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val store = (cmd === M_XWR)
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val load = (cmd === M_XRD)
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val amo = cmd(3).toBool
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val read = load || amo || (cmd === M_PFR) || (cmd === M_PFW)
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val write = store || amo
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(read, write)
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}
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}
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trait CoherencePolicy { }
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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val X_INIT_READ_SHARED = UFix(0, 2)
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val X_INIT_READ_EXCLUSIVE = UFix(1, 2)
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val X_INIT_WRITE_UNCACHED = UFix(3, 2)
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val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
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val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
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val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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( state === tileClean || state === tileDirty)
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnCacheControl(cmd: Bits) = tileInvalid
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def newState(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileDirty, tileClean)
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, has_data: Bool): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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reply.p_type := P_REP_INVALIDATE_ACK
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reply.global_xact_id := UFix(0)
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reply
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}
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.t_type === X_INIT_WRITE_UNCACHED)
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}
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trait FourStateCoherence extends CoherencePolicy {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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val X_INIT_READ_SHARED = UFix(0, X_INIT_TYPE_BITS)
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val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS)
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val X_INIT_READ_UNCACHED = UFix(2, X_INIT_TYPE_BITS)
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val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS)
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val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
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val X_REP_READ_UNCACHED = UFix(2, X_REP_TYPE_BITS)
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val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS)
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val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS)
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val P_REQ_DOWNGRADE = UFix(1, P_REQ_TYPE_BITS)
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val P_REQ_COPY = UFix(2, P_REQ_TYPE_BITS)
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val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS)
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val P_REP_DOWNGRADE_DATA = UFix(1, P_REP_TYPE_BITS)
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val P_REP_COPY_DATA = UFix(2, P_REP_TYPE_BITS)
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val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
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val P_REP_DOWNGRADE_ACK = UFix(4, P_REP_TYPE_BITS)
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val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
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(state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) ||
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(write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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MuxLookup(cmd, (state === tileExclusiveDirty), Array(
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M_INV -> (state === tileExclusiveDirty),
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M_CLN -> (state === tileExclusiveDirty)
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))
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}
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def needsWriteback (state: UFix): Bool = {
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needsTransactionOnCacheControl(M_INV, state)
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileExclusiveDirty, state)
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}
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def newStateOnCacheControl(cmd: Bits) = {
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MuxLookup(cmd, tileInvalid, Array(
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M_INV -> tileInvalid,
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M_CLN -> tileExclusiveClean
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))
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}
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def newStateOnWriteback() = newStateOnCacheControl(M_INV)
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def newStateOnFlush() = newStateOnCacheControl(M_INV)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.t_type, tileInvalid, Array(
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X_REP_READ_SHARED -> tileShared,
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X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
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X_REP_READ_EXCLUSIVE_ACK -> tileExclusiveDirty,
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X_REP_READ_UNCACHED -> tileInvalid,
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X_REP_WRITE_UNCACHED -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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probeInvalidate -> tileInvalid,
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probeDowngrade -> tileShared,
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probeCopy -> state
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))
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}
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
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}
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = X_INIT_WRITE_UNCACHED
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val with_data = MuxLookup(incoming.p_type, P_REP_INVALIDATE_DATA, Array(
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probeInvalidate -> P_REP_INVALIDATE_DATA,
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probeDowngrade -> P_REP_DOWNGRADE_DATA,
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probeCopy -> P_REP_COPY_DATA
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))
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val without_data = MuxLookup(incoming.p_type, P_REP_INVALIDATE_ACK, Array(
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probeInvalidate -> P_REP_INVALIDATE_ACK,
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probeDowngrade -> P_REP_DOWNGRADE_ACK,
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probeCopy -> P_REP_COPY_ACK
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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reply
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}
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def hasData (reply: ProbeReply): Bool = {
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(reply.p_type === P_REP_INVALIDATE_DATA ||
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reply.p_type === P_REP_DOWNGRADE_DATA ||
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reply.p_type === P_REP_COPY_DATA)
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}
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def hasData (init: TransactionInit): Bool = {
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(init.t_type === X_INIT_WRITE_UNCACHED)
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}
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def hasData (reply: TransactionReply): Bool = {
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(reply.t_type != X_REP_WRITE_UNCACHED && reply.t_type != X_REP_READ_EXCLUSIVE_ACK)
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}
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
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MuxLookup(t_type, X_REP_READ_UNCACHED, Array(
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X_INIT_READ_SHARED -> Mux(count > UFix(0), X_REP_READ_SHARED, X_REP_READ_EXCLUSIVE),
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X_INIT_READ_EXCLUSIVE -> X_REP_READ_EXCLUSIVE,
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X_INIT_READ_UNCACHED -> X_REP_READ_UNCACHED,
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X_INIT_WRITE_UNCACHED -> X_REP_WRITE_UNCACHED
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))
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}
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def getProbeRequestType(t_type: UFix, global_state: UFix): UFix = {
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MuxLookup(t_type, P_REQ_COPY, Array(
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X_INIT_READ_SHARED -> P_REQ_DOWNGRADE,
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X_INIT_READ_EXCLUSIVE -> P_REQ_INVALIDATE,
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X_INIT_READ_UNCACHED -> P_REQ_COPY,
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X_INIT_WRITE_UNCACHED -> P_REQ_INVALIDATE
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))
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}
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def needsMemRead(t_type: UFix, global_state: UFix): Bool = {
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(t_type != X_INIT_WRITE_UNCACHED)
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}
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def needsMemWrite(t_type: UFix, global_state: UFix): Bool = {
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(t_type === X_INIT_WRITE_UNCACHED)
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}
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def needsAckReply(t_type: UFix, global_state: UFix): Bool = {
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(t_type === X_INIT_WRITE_UNCACHED)
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}
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}
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