88 lines
2.4 KiB
Scala
88 lines
2.4 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Instructions._
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object ALU
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{
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val SZ_ALU_FN = 4
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val FN_X = Bits("b????")
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val FN_ADD = Bits(0)
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val FN_SL = Bits(1)
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val FN_XOR = Bits(4)
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val FN_OR = Bits(6)
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val FN_AND = Bits(7)
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val FN_SR = Bits(5)
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val FN_SEQ = Bits(8)
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val FN_SNE = Bits(9)
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val FN_SUB = Bits(10)
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val FN_SRA = Bits(11)
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val FN_SLT = Bits(12)
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val FN_SGE = Bits(13)
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val FN_SLTU = Bits(14)
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val FN_SGEU = Bits(15)
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val FN_DIV = FN_XOR
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val FN_DIVU = FN_SR
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val FN_REM = FN_OR
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val FN_REMU = FN_AND
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val FN_MUL = FN_ADD
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val FN_MULH = FN_SL
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val FN_MULHSU = FN_SLT
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val FN_MULHU = FN_SLTU
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def isMulFN(fn: Bits, cmp: Bits) = fn(1,0) === cmp(1,0)
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def isSub(cmd: Bits) = cmd(3)
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def cmpUnsigned(cmd: Bits) = cmd(1)
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def cmpInverted(cmd: Bits) = cmd(0)
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def cmpEq(cmd: Bits) = !cmd(2)
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}
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import ALU._
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class ALUIO extends Bundle {
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val dw = Bits(INPUT, SZ_DW)
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val fn = Bits(INPUT, SZ_ALU_FN)
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val in2 = UInt(INPUT, params(XprLen))
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val in1 = UInt(INPUT, params(XprLen))
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val out = UInt(OUTPUT, params(XprLen))
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val adder_out = UInt(OUTPUT, params(XprLen))
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}
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class ALU extends Module
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{
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val io = new ALUIO
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// ADD, SUB
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val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2)
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// SLT, SLTU
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val cmp = cmpInverted(io.fn) ^
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Mux(cmpEq(io.fn), sum === UInt(0),
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Mux(io.in1(63) === io.in2(63), sum(63),
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Mux(cmpUnsigned(io.fn), io.in2(63), io.in1(63))))
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// SLL, SRL, SRA
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val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUInt
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val shin_hi_32 = Mux(isSub(io.fn), Fill(32, io.in1(31)), UInt(0,32))
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val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
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val shin_r = Cat(shin_hi, io.in1(31,0))
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val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r))
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val shout_r = (Cat(isSub(io.fn) & shin(63), shin).toSInt >> shamt)(63,0)
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val shout_l = Reverse(shout_r)
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val out64 =
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Mux(io.fn === FN_ADD || io.fn === FN_SUB, sum,
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Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r,
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Mux(io.fn === FN_SL, shout_l,
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Mux(io.fn === FN_AND, io.in1 & io.in2,
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Mux(io.fn === FN_OR, io.in1 | io.in2,
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Mux(io.fn === FN_XOR, io.in1 ^ io.in2,
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/* all comparisons */ cmp))))))
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val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
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io.out := Cat(out_hi, out64(31,0)).toUInt
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io.adder_out := sum
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}
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