93b2fa197e
* build: stop using empty .prm file * generator: general-purpose mechanism for creating elaboration artefacts
53 lines
2.4 KiB
Plaintext
53 lines
2.4 KiB
Plaintext
#--------------------------------------------------------------------
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# Verilog Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(long_name).fir
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verilog = $(generated_dir)/$(long_name).v
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# If I don't mark these as .SECONDARY then make will delete these internal
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# files.
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.SECONDARY: $(firrtl) $(verilog)
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$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
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cd $(generated_dir) && \
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rm -f $@ && \
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$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
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mv $@.tmp $@
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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$(output_dir)/%.run: $(output_dir)/% $(simv)
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cd $(sim_dir) && $(exec_simv) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.out: $(output_dir)/% $(simv)
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cd $(sim_dir) && $(exec_simv) +verbose +max-cycles=$(timeout_cycles) $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vcd: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.saif: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
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run: run-asm-tests run-bmark-tests
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run-debug: run-asm-tests-debug run-bmark-tests-debug
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run-fast: run-asm-tests-fast run-bmark-tests-fast
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.PHONY: run-asm-tests run-bmark-tests
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.PHONY: run-asm-tests-debug run-bmark-tests-debug
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.PHONY: run run-debug run-fast
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junk += $(output_dir)
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