50 lines
1.2 KiB
Scala
50 lines
1.2 KiB
Scala
// See LICENSE.Berkeley for license details.
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package util
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import Chisel._
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/** This black-boxes a Clock Divider by 2.
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* The output clock is phase-aligned to the input clock.
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* If you use this in synthesis, make sure your sdc
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* declares that you want it to do the same.
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*
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* Because Chisel does not support
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* blocking assignments, it is impossible
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* to create a deterministic divided clock.
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*/
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class ClockDivider2 extends BlackBox {
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val io = new Bundle {
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val clk_out = Clock(OUTPUT)
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val clk_in = Clock(INPUT)
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}
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}
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class ClockDivider3 extends BlackBox {
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val io = new Bundle {
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val clk_out = Clock(OUTPUT)
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val clk_in = Clock(INPUT)
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}
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}
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/** Divide the clock by power of 2 times.
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* @param pow2 divides the clock 2 ^ pow2 times
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* WARNING: This is meant for simulation use only. */
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class Pow2ClockDivider(pow2: Int) extends Module {
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val io = new Bundle {
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val clock_out = Clock(OUTPUT)
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}
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if (pow2 == 0) {
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io.clock_out := clock
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} else {
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val dividers = Seq.fill(pow2) { Module(new ClockDivider2) }
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dividers.init.zip(dividers.tail).map { case (last, next) =>
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next.io.clk_in := last.io.clk_out
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}
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dividers.head.io.clk_in := clock
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io.clock_out := dividers.last.io.clk_out
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}
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}
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