1
0
rocket-chip/.travis.yml
Howard Mao c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00

77 lines
1.8 KiB
YAML

language: scala
# run on new infrastructure
sudo: false
cache:
apt: true
directories:
$HOME/.ivy2
regression/install
chisel/target
context-dependent-environments/target
groundtest/target
hardfloat/target
junctions/target
project/project/target
project/target
rocket/target
target
uncore/target
zscale/target
# packages needed to build riscv-tools
addons:
apt:
sources:
- ubuntu-toolchain-r-test
packages:
- gcc-4.8
- g++-4.8
- gperf
- autoconf
- automake
- autotools-dev
- libmpc-dev
- libmpfr-dev
- libgmp-dev
- gawk
- build-essential
- bison
- flex
- texinfo
env:
matrix:
- CONFIG=DefaultConfig
- CONFIG=DefaultL2Config
- CONFIG=RoccExampleConfig
- CONFIG=DualCoreConfig
- CONFIG=MemtestConfig
- CONFIG=FancyMemtestConfig
- CONFIG=MemoryMuxMemtestConfig
- CONFIG=BroadcastRegressionTestConfig
- CONFIG=CacheRegressionTestConfig
- CONFIG=NastiConverterTestConfig
- CONFIG=UnitTestConfig
- CONFIG=SplitL2MetadataTestConfig
# blacklist private branches
branches:
except:
- hwacha
- boom
- hurricane
before_install:
- rm riscv-tools/.travis.yml
- export CXX=g++-4.8 CC=gcc-4.8
script:
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-bmark-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default -j1
before_cache:
- ls -tr regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf