52 lines
1.3 KiB
C++
52 lines
1.3 KiB
C++
#ifndef _MM_EMULATOR_DRAMSIM2_H
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#define _MM_EMULATOR_DRAMSIM2_H
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#include "mm.h"
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#include <DRAMSim.h>
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#include <map>
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#include <queue>
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#include <stdint.h>
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class mm_dramsim2_t : public mm_t
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{
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public:
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mm_dramsim2_t() : store_inflight(false), store_count(0) {}
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virtual void init(size_t sz, int word_size, int line_size);
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virtual bool req_cmd_ready() { return mem->willAcceptTransaction() && !store_inflight; }
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virtual bool req_data_ready() { return mem->willAcceptTransaction() && store_inflight; }
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virtual bool resp_valid() { return !resp.empty(); }
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virtual uint64_t resp_tag() { return resp_valid() ? resp.front().first : 0; }
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virtual void* resp_data() { return resp_valid() ? &resp.front().second[0] : &dummy_data[0]; }
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virtual void tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits,
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bool resp_rdy
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);
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protected:
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DRAMSim::MultiChannelMemorySystem *mem;
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uint64_t cycle;
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bool store_inflight;
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int store_count;
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uint64_t store_addr;
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std::vector<char> dummy_data;
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std::map<uint64_t,uint64_t> req;
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std::queue<std::pair<uint64_t, std::vector<char>>> resp;
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void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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void write_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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};
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#endif
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