49 lines
1.7 KiB
Scala
49 lines
1.7 KiB
Scala
// See LICENSE for license details.
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package uncore
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package constants
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import Chisel._
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object MemoryOpConstants extends MemoryOpConstants
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trait MemoryOpConstants {
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val MT_SZ = 3
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val MT_X = Bits("b???")
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val MT_B = Bits("b000")
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val MT_H = Bits("b001")
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val MT_W = Bits("b010")
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val MT_D = Bits("b011")
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val MT_BU = Bits("b100")
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val MT_HU = Bits("b101")
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val MT_WU = Bits("b110")
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val NUM_XA_OPS = 9
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val M_SZ = 5
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val M_X = Bits("b?????");
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val M_XRD = Bits("b00000"); // int load
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val M_XWR = Bits("b00001"); // int store
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val M_PFR = Bits("b00010"); // prefetch with intent to read
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val M_PFW = Bits("b00011"); // prefetch with intent to write
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val M_XA_SWAP = Bits("b00100");
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val M_NOP = Bits("b00101");
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val M_XLR = Bits("b00110");
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val M_XSC = Bits("b00111");
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val M_XA_ADD = Bits("b01000");
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val M_XA_XOR = Bits("b01001");
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val M_XA_OR = Bits("b01010");
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val M_XA_AND = Bits("b01011");
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val M_XA_MIN = Bits("b01100");
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val M_XA_MAX = Bits("b01101");
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val M_XA_MINU = Bits("b01110");
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val M_XA_MAXU = Bits("b01111");
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val M_FLUSH = Bits("b10000") // write back dirty data and cede R/W permissions
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val M_PRODUCE = Bits("b10001") // write back dirty data and cede W permissions
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val M_CLEAN = Bits("b10011") // write back dirty data and retain R/W permissions
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def isAMO(cmd: Bits) = cmd(3) || cmd === M_XA_SWAP
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def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
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def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd)
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def isWrite(cmd: Bits) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
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def isWriteIntent(cmd: Bits) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
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}
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