db9de94588
This uses the new SCRFile changes to generate a header file containing a list of all the SCRs in a core to remove the magic constant "63" (the HTIF clock divider control register) and replace it with a generated number (which is still 63).
103 lines
3.6 KiB
Scala
103 lines
3.6 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.Parameters
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import junctions._
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import uncore._
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class MemDessert(topParams: Parameters) extends Module {
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implicit val p = topParams
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val io = new MemDesserIO(p(HtifKey).width)
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val x = Module(new MemDesser(p(HtifKey).width))
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x.io.narrow <> io.narrow
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io.wide <> x.io.wide
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}
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object VLSIUtils {
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def doOuterMemorySystemSerdes(
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llcs: Seq[NastiIO],
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mems: Seq[NastiIO],
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backup: MemSerializedIO,
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en: Bool,
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nMemChannels: Int,
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htifWidth: Int,
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blockOffsetBits: Int)
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(implicit p: Parameters) {
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val arb = Module(new NastiArbiter(nMemChannels))
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val conv = Module(new MemIONastiIOConverter(blockOffsetBits))
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val mem_serdes = Module(new MemSerdes(htifWidth))
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conv.io.nasti <> arb.io.slave
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mem_serdes.io.wide <> conv.io.mem
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backup <> mem_serdes.io.narrow
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llcs zip mems zip arb.io.master foreach { case ((llc, mem), wide) =>
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llc.ar.ready := Mux(en, wide.ar.ready, mem.ar.ready)
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mem.ar.valid := llc.ar.valid && !en
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mem.ar.bits := llc.ar.bits
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wide.ar.valid := llc.ar.valid && en
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wide.ar.bits := llc.ar.bits
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llc.aw.ready := Mux(en, wide.aw.ready, mem.aw.ready)
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mem.aw.valid := llc.aw.valid && !en
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mem.aw.bits := llc.aw.bits
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wide.aw.valid := llc.aw.valid && en
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wide.aw.bits := llc.aw.bits
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llc.w.ready := Mux(en, wide.w.ready, mem.w.ready)
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mem.w.valid := llc.w.valid && !en
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mem.w.bits := llc.w.bits
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wide.w.valid := llc.w.valid && en
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wide.w.bits := llc.w.bits
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llc.b.valid := Mux(en, wide.b.valid, mem.b.valid)
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llc.b.bits := Mux(en, wide.b.bits, mem.b.bits)
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mem.b.ready := llc.b.ready && !en
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wide.b.ready := llc.b.ready && en
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llc.r.valid := Mux(en, wide.r.valid, mem.r.valid)
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llc.r.bits := Mux(en, wide.r.bits, mem.r.bits)
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mem.r.ready := llc.r.ready && !en
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wide.r.ready := llc.r.ready && en
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}
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}
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def padOutHTIFWithDividedClock(
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htif: HostIO,
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scr: SCRIO,
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child: MemSerializedIO,
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parent: MemBackupCtrlIO,
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host: HostIO,
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htifW: Int) {
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val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
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hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
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hio.io.set_divisor.bits := scr.wdata
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scr.rdata(63) := hio.io.divisor
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scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR")
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hio.io.out_fast.valid := htif.out.valid || child.req.valid
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hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))
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htif.out.ready := hio.io.out_fast.ready
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child.req.ready := hio.io.out_fast.ready && !htif.out.valid
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host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
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host.out.bits := hio.io.out_slow.bits
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parent.out_valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
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hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.out_ready)
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val mem_backup_resp_valid = parent.en && parent.in_valid
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hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid
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hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits)
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host.in.ready := hio.io.in_slow.ready
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child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
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child.resp.bits := hio.io.in_fast.bits
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htif.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
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htif.in.bits := hio.io.in_fast.bits
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hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.in.ready)
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host.clk := hio.io.clk_slow
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host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
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}
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}
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