224 lines
12 KiB
Scala
224 lines
12 KiB
Scala
package referencechip
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import Chisel._
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import uncore._
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import scala.reflect._
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object TileLinkHeaderAppender {
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def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
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val shim = Module(new TileLinkHeaderAppender(in.meta.bits.payload, in.data.bits.payload, clientId, nBanks, addrConvert))
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shim.io.in <> in
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shim.io.out
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}
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def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
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val shim = Module(new TileLinkHeaderAppender(in.bits.payload.clone, new AcquireData, clientId, nBanks, addrConvert))
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shim.io.in.meta <> in
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shim.io.out.meta
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}
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}
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class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module {
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implicit val ln = conf.ln
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val io = new Bundle {
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val in = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip
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val out = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType))
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}
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val meta_q = Queue(io.in.meta)
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val data_q = Queue(io.in.data)
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if(nBanks == 1) {
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io.out.meta.bits.payload := meta_q.bits.payload
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io.out.meta.bits.header.src := UInt(clientId)
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io.out.meta.bits.header.dst := UInt(0)
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io.out.meta.valid := meta_q.valid
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meta_q.ready := io.out.meta.ready
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io.out.data.bits.payload := data_q.bits.payload
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io.out.data.bits.header.src := UInt(clientId)
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io.out.data.bits.header.dst := UInt(0)
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io.out.data.valid := data_q.valid
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data_q.ready := io.out.data.ready
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} else {
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val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
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val addr_q = Module(new Queue(io.in.meta.bits.payload.addr.clone, 2, pipe = true, flow = true))
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val data_cnt = Reg(init=UInt(0, width = log2Up(REFILL_CYCLES)))
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val data_cnt_up = data_cnt + UInt(1)
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io.out.meta.bits.payload := meta_q.bits.payload
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io.out.meta.bits.header.src := UInt(clientId)
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io.out.meta.bits.header.dst := addrConvert(meta_q.bits.payload.addr)
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io.out.data.bits.payload := meta_q.bits.payload
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io.out.data.bits.header.src := UInt(clientId)
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io.out.data.bits.header.dst := addrConvert(addr_q.io.deq.bits)
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addr_q.io.enq.bits := meta_q.bits.payload.addr
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io.out.meta.valid := meta_q.valid && addr_q.io.enq.ready
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meta_q.ready := io.out.meta.ready && addr_q.io.enq.ready
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io.out.data.valid := data_q.valid && addr_q.io.deq.valid
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data_q.ready := io.out.data.ready && addr_q.io.deq.valid
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addr_q.io.enq.valid := meta_q.valid && io.out.meta.ready && meta_has_data
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addr_q.io.deq.ready := Bool(false)
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when(data_q.valid && data_q.ready) {
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data_cnt := data_cnt_up
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when(data_cnt_up === UInt(0)) {
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addr_q.io.deq.ready := Bool(true)
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}
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}
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}
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}
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//Adapter betweewn an UncachedTileLinkIO and a mem controller MemIO
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class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfiguration) extends Module {
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val io = new Bundle {
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val uncached = new UncachedTileLinkIO().flip
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val mem = new ioMem
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}
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val mem_cmd_q = Module(new Queue(new MemReqCmd, qDepth))
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val mem_data_q = Module(new Queue(new MemData, qDepth))
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mem_cmd_q.io.enq.valid := io.uncached.acquire.meta.valid
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io.uncached.acquire.meta.ready := mem_cmd_q.io.enq.ready
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mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.meta.bits.payload.a_type, UInt(0))
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mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.meta.bits.payload.client_xact_id
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mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.meta.bits.payload.addr
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mem_data_q.io.enq.valid := io.uncached.acquire.data.valid
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io.uncached.acquire.data.ready := mem_data_q.io.enq.ready
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mem_data_q.io.enq.bits.data := io.uncached.acquire.data.bits.payload.data
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io.uncached.grant.valid := io.mem.resp.valid
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io.mem.resp.ready := io.uncached.grant.ready
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io.uncached.grant.bits.payload.data := io.mem.resp.bits.data
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io.uncached.grant.bits.payload.client_xact_id := io.mem.resp.bits.tag
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io.uncached.grant.bits.payload.master_xact_id := UInt(0) // DNC
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io.uncached.grant.bits.payload.g_type := UInt(0) // DNC
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io.mem.req_cmd <> mem_cmd_q.io.deq
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io.mem.req_data <> mem_data_q.io.deq
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}
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class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}}))
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implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
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// Aliases for the various network IO bundle types
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type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
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type PBCIO[M <: Data, D <: Data] = PairedDataIO[PhysicalNetworkIO[M], PhysicalNetworkIO[D]]
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type PLNIO[M <: Data, D <: Data] = PairedDataIO[LogicalNetworkIO[M], LogicalNetworkIO[D]]
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type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
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type ToCrossbar[T <: Data] = FLNIO[T] => FBCIO[T]
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// Shims for converting between logical network IOs and physical network IOs
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//TODO: Could be less verbose if you could override subbundles after a <>
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def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = Decoupled(new LogicalNetworkIO(in.bits.payload)).asDirectionless
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = DefaultFromCrossbarShim(in)
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out.bits.header.src := in.bits.header.src - UInt(ln.nMasters)
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out
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}
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def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = DefaultFromCrossbarShim(in)
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out.bits.header.dst := in.bits.header.dst - UInt(ln.nMasters)
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out
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}
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def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = Decoupled(new PhysicalNetworkIO(in.bits.payload)).asDirectionless
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = DefaultToCrossbarShim(in)
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out.bits.header.dst := in.bits.header.dst + UInt(ln.nMasters)
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out
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}
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def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = DefaultToCrossbarShim(in)
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out.bits.header.src := in.bits.header.src + UInt(ln.nMasters)
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out
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}
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// Make an individual connection between virtual and physical ports using
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// a particular shim. Also seal the unused FIFO control signal.
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def doFIFOInputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: ToCrossbar[T]) = {
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val s = shim(log_io)
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phys_in.valid := s.valid
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phys_in.bits := s.bits
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s.ready := phys_in.ready
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phys_out.ready := Bool(false)
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}
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def doFIFOOutputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: FromCrossbar[T]) = {
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val s = shim(phys_out)
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log_io.valid := s.valid
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log_io.bits := s.bits
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s.ready := log_io.ready
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phys_in.valid := Bool(false)
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}
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// Use reflection to determine whether a particular endpoint should be
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// hooked up as an [input/output] for a FIFO nework that is transmiitting
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// [client/master]-sourced messages.
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def doFIFOHookup[S <: CoherenceAgentRole: ClassTag, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
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// Is end's type a subtype of S, the agent type associated with inputs?
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if(classTag[S].runtimeClass.isInstance(end))
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doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
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else
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doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
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}
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def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
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doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim)
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def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
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doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim)
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// Use reflection to determine whether a particular endpoint should be
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// hooked up as an [input/output] for a Paired nework that is transmiitting
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// [client/master]-sourced messages.
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def doPairedDataHookup[S <: CoherenceAgentRole : ClassTag, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
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// Is end's type a subtype of S, the agent type associated with inputs?
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if(classTag[S].runtimeClass.isInstance(end)) {
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doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
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doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
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} else {
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doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
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doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
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}
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}
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def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
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doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim)
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def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
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doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim)
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// Actually instantiate the particular networks required for TileLink
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def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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val acq_net = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, acqHasData _))
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
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def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload)
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val rel_net = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, relHasData _))
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
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val probe_net = Module(new BasicCrossbar(new Probe))
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
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val grant_net = Module(new BasicCrossbar(new Grant))
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
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val ack_net = Module(new BasicCrossbar(new GrantAck))
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
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val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
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}
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