ed827678ac
This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
49 lines
1.8 KiB
Scala
49 lines
1.8 KiB
Scala
import sbt._
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import Keys._
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import complete._
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import complete.DefaultParsers._
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import xerial.sbt.Pack._
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object BuildSettings extends Build {
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override lazy val settings = super.settings ++ Seq(
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organization := "berkeley",
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version := "1.2",
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scalaVersion := "2.11.7",
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parallelExecution in Global := false,
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traceLevel := 15,
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scalacOptions ++= Seq("-deprecation","-unchecked"),
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libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)
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)
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lazy val chisel = project in file("chisel3")
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lazy val cde = project in file("context-dependent-environments")
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lazy val hardfloat = project.dependsOn(chisel)
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lazy val junctions = project.dependsOn(chisel, cde)
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lazy val uncore = project.dependsOn(junctions)
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lazy val rocket = project.dependsOn(hardfloat, uncore)
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lazy val groundtest = project.dependsOn(rocket)
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lazy val coreplex = project.dependsOn(groundtest)
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lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(coreplex)
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lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
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lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
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val setMake = NotSpace ~ ( Space ~> NotSpace )
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val chipSettings = packAutoSettings ++ Seq(
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addons := {
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val a = sys.env.getOrElse("ROCKETCHIP_ADDONS", "")
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println(s"Using addons: $a")
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a.split(" ")
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},
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unmanagedSourceDirectories in Compile ++= addons.value.map(baseDirectory.value / _ / "src/main/scala"),
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mainClass in (Compile, run) := Some("rocketchip.RocketChipGenerator"),
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make := {
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val jobs = java.lang.Runtime.getRuntime.availableProcessors
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val (makeDir, target) = setMake.parsed
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(run in Compile).evaluated
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s"make -C $makeDir -j $jobs $target" !
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}
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)
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}
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