130 lines
3.9 KiB
Scala
130 lines
3.9 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import uncore._
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import Util._
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case object RoccMaxTaggedMemXacts extends Field[Int]
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case object RoccNMemChannels extends Field[Int]
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class RoCCInstruction extends Bundle
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{
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val funct = Bits(width = 7)
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val rs2 = Bits(width = 5)
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val rs1 = Bits(width = 5)
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val xd = Bool()
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val xs1 = Bool()
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val xs2 = Bool()
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val rd = Bits(width = 5)
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val opcode = Bits(width = 7)
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}
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class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) {
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val inst = new RoCCInstruction
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val rs1 = Bits(width = xLen)
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val rs2 = Bits(width = xLen)
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}
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class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
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val rd = Bits(width = 5)
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val data = Bits(width = xLen)
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}
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class RoCCInterface(implicit p: Parameters) extends Bundle {
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val cmd = Decoupled(new RoCCCommand).flip
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val resp = Decoupled(new RoCCResponse)
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val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
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val busy = Bool(OUTPUT)
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val s = Bool(INPUT)
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val interrupt = Bool(OUTPUT)
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// These should be handled differently, eventually
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val imem = new ClientUncachedTileLinkIO
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val dmem = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
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val iptw = new TLBPTWIO
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val dptw = new TLBPTWIO
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val pptw = new TLBPTWIO
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val exception = Bool(INPUT)
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}
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abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
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val io = new RoCCInterface
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io.mem.req.bits.phys := Bool(true) // don't perform address translation
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}
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class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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val regfile = Mem(UInt(width = xLen), n)
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val busy = Reg(init=Vec(Bool(false), n))
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val cmd = Queue(io.cmd)
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val funct = cmd.bits.inst.funct
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val addr = cmd.bits.inst.rs2(log2Up(n)-1,0)
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val doWrite = funct === UInt(0)
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val doRead = funct === UInt(1)
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val doLoad = funct === UInt(2)
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val doAccum = funct === UInt(3)
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val memRespTag = io.mem.resp.bits.tag(log2Up(n)-1,0)
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// datapath
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val addend = cmd.bits.rs1
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val accum = regfile(addr)
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val wdata = Mux(doWrite, addend, accum + addend)
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when (cmd.fire() && (doWrite || doAccum)) {
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regfile(addr) := wdata
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}
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when (io.mem.resp.valid) {
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regfile(memRespTag) := io.mem.resp.bits.data
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}
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// control
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when (io.mem.req.fire()) {
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busy(addr) := Bool(true)
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}
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when (io.mem.resp.valid) {
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busy(memRespTag) := Bool(false)
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}
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val doResp = cmd.bits.inst.xd
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val stallReg = busy(addr)
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val stallLoad = doLoad && !io.mem.req.ready
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val stallResp = doResp && !io.resp.ready
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cmd.ready := !stallReg && !stallLoad && !stallResp
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// command resolved if no stalls AND not issuing a load that will need a request
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// PROC RESPONSE INTERFACE
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io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
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// valid response if valid command, need a response, and no stalls
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io.resp.bits.rd := cmd.bits.inst.rd
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// Must respond with the appropriate tag or undefined behavior
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io.resp.bits.data := accum
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// Semantics is to always send out prior accumulator register value
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io.busy := cmd.valid || busy.reduce(_||_)
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// Be busy when have pending memory requests or committed possibility of pending requests
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io.interrupt := Bool(false)
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// Set this true to trigger an interrupt on the processor (please refer to supervisor documentation)
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// MEMORY REQUEST INTERFACE
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io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
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io.mem.req.bits.addr := addend
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io.mem.req.bits.tag := addr
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io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
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io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
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io.mem.req.bits.data := Bits(0) // we're not performing any stores...
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io.mem.invalidate_lr := false
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io.imem.acquire.valid := false
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io.imem.grant.ready := false
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io.dmem.head.acquire.valid := false
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io.dmem.head.grant.ready := false
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io.iptw.req.valid := false
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io.dptw.req.valid := false
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io.pptw.req.valid := false
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}
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