| .. |
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Arbiter.scala
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copyright: ran scripts/modify-copyright
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2016-11-27 22:15:43 -08:00 |
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AsyncCrossing.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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AtomicAutomata.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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Broadcast.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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Buffer.scala
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TLBuffer: move TLBufferParams to diplomacy.BufferParams
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2017-03-16 15:19:36 -07:00 |
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Bundles.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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CacheCork.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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Delayer.scala
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TLDelayer: insert noise on invalid cycles
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2017-03-11 02:53:43 -08:00 |
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Edges.scala
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tilelink2: define is{Request,Response} based on spec
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2017-03-20 13:41:02 -07:00 |
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Example.scala
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uncore: add DTS meta-data for devices
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2017-03-02 21:19:22 -08:00 |
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FIFOFixer.scala
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FIFOFixer: Not all D-channel messages are A-channel responses
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2017-03-21 14:17:38 -07:00 |
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Filter.scala
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uncore: switch to new diplomacy Node API
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2017-01-29 15:54:45 -08:00 |
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Fragmenter.scala
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Fragmenter: fix a bug when underlying device supports larger bursts (#589)
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2017-03-17 11:00:49 -07:00 |
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Fuzzer.scala
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LFSR: use random intial value of the start register
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2017-03-13 13:17:52 -07:00 |
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HintHandler.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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IntNodes.scala
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IntXing: support configurable sync depth
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2017-03-02 21:19:23 -08:00 |
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Isolation.scala
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tilelink2: split suportsAcquire into T and B variants
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2017-01-19 19:07:13 -08:00 |
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Legacy.scala
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diplomacy: make config.Parameters available in bundle connect()
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2016-12-07 12:24:01 -08:00 |
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Metadata.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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Monitor.scala
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Monitor: support early ack
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2017-03-20 14:49:19 -07:00 |
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Nodes.scala
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diplomacy: use HeterogeneousBag instead of Vec
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2017-02-22 17:05:22 -08:00 |
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package.scala
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Standardize Data.holdUnless and SeqMem.readAndHold
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2017-02-25 03:07:49 -08:00 |
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Parameters.scala
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tilelink2: add client-side FIFO parameterization
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2017-03-21 11:16:51 -07:00 |
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RAMModel.scala
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tilelink2 RAMModel: weaken fifo requirement check
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2017-03-21 11:16:51 -07:00 |
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RationalCrossing.scala
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TLRational: test all corners
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2017-02-17 14:44:31 +01:00 |
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RegisterRouter.scala
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RegisterRouter: support devices with gaps
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2017-03-20 14:49:22 -07:00 |
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RegisterRouterTest.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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Repeater.scala
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copyright: ran scripts/modify-copyright
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2016-11-27 22:15:43 -08:00 |
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SourceShrinker.scala
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tilelink2 SourceShrinker: destroy FIFO behaviour
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2017-03-21 11:16:51 -07:00 |
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SRAM.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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TestRAM.scala
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tileink2: add a TestRAM; a zero-delay RAM useful for testing
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2017-03-14 14:06:17 -07:00 |
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ToAHB.scala
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ToAHB: appease AHB VIP
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2017-03-16 15:17:05 -07:00 |
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ToAPB.scala
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TLToAPB: use the now standard aFlow parameter name
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2017-03-16 15:34:59 -07:00 |
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ToAXI4.scala
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Make parameters for TLToAHB and TLToAXI4 accessable (#581)
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2017-03-10 22:26:38 -08:00 |
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WidthWidget.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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Xbar.scala
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tilelink2 Xbar: don't use unnecessary ports
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2017-03-19 17:02:24 -07:00 |
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Zero.scala
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uncore: add DTS meta-data for devices
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2017-03-02 21:19:22 -08:00 |
