102 lines
2.4 KiB
Scala
102 lines
2.4 KiB
Scala
// See LICENSE.SiFive for license details.
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// If you know two clocks are related with a N:1 or 1:N relationship, you
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// can cross the clock domains with lower latency than an AsyncQueue. This
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// crossing adds 1 cycle in the target clock domain.
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package util
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import Chisel._
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final class RationalIO[T <: Data](gen: T) extends Bundle
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{
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val bits = gen.chiselCloneType
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val valid = Bool()
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val source = UInt(width = 2)
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val ready = Bool().flip
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val sink = UInt(width = 2).flip
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override def cloneType: this.type = new RationalIO(gen).asInstanceOf[this.type]
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}
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object RationalIO
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{
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def apply[T <: Data](gen: T) = new RationalIO(gen)
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}
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class RationalCrossingSource[T <: Data](gen: T) extends Module
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{
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val io = new Bundle {
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val enq = DecoupledIO(gen).flip
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val deq = RationalIO(gen)
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}
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val enq = Queue(io.enq, 1, flow=true)
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val deq = io.deq
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val count = RegInit(UInt(0, width = 2))
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val equal = count === deq.sink
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deq.valid := enq.valid
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deq.source := count
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deq.bits := Mux(equal, enq.bits, RegEnable(enq.bits, equal))
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enq.ready := Mux(equal, deq.ready, count(1) =/= deq.sink(0))
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when (enq.fire()) { count := Cat(count(0), !count(1)) }
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}
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class RationalCrossingSink[T <: Data](gen: T) extends Module
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{
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val io = new Bundle {
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val enq = RationalIO(gen).flip
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val deq = DecoupledIO(gen)
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}
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val enq = io.enq
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val deq = Wire(io.deq)
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io.deq <> Queue(deq, 1, pipe=true)
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val count = RegInit(UInt(0, width = 2))
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val equal = count === enq.source
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enq.ready := deq.ready
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enq.sink := count
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deq.bits := enq.bits
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deq.valid := Mux(equal, enq.valid, count(1) =/= enq.source(0))
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when (deq.fire()) { count := Cat(count(0), !count(1)) }
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}
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class RationalCrossing[T <: Data](gen: T) extends Module
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{
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val io = new CrossingIO(gen)
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val source = Module(new RationalCrossingSource(gen))
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val sink = Module(new RationalCrossingSink(gen))
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source.clock := io.enq_clock
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source.reset := io.enq_reset
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sink .clock := io.deq_clock
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sink .reset := io.deq_reset
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source.io.enq <> io.enq
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io.deq <> sink.io.deq
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}
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object ToRational
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{
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def apply[T <: Data](x: DecoupledIO[T]): RationalIO[T] = {
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val source = Module(new RationalCrossingSource(x.bits))
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source.io.enq <> x
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source.io.deq
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}
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}
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object FromRational
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{
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def apply[T <: Data](x: RationalIO[T]): DecoupledIO[T] = {
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val sink = Module(new RationalCrossingSink(x.bits))
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sink.io.enq <> x
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sink.io.deq
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}
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}
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