263 lines
8.4 KiB
Scala
263 lines
8.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.util.{ReadyValidIO}
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import diplomacy._
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import util._
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abstract class TLBundleBase(params: TLBundleParameters) extends GenericParameterizedBundle(params)
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// common combos in lazy policy:
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// Put + Acquire
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// Release + AccessAck
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object TLMessages
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{
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// A B C D E
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val PutFullData = UInt(0) // . . => AccessAck
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val PutPartialData = UInt(1) // . . => AccessAck
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val ArithmeticData = UInt(2) // . . => AccessAckData
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val LogicalData = UInt(3) // . . => AccessAckData
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val Get = UInt(4) // . . => AccessAckData
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val Hint = UInt(5) // . . => HintAck
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val Acquire = UInt(6) // . => Grant[Data]
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val Probe = UInt(6) // . => ProbeAck[Data]
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val AccessAck = UInt(0) // . .
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val AccessAckData = UInt(1) // . .
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val HintAck = UInt(2) // . .
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val ProbeAck = UInt(4) // .
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val ProbeAckData = UInt(5) // .
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val Release = UInt(6) // . => ReleaseAck
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val ReleaseData = UInt(7) // . => ReleaseAck
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val Grant = UInt(4) // . => GrantAck
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val GrantData = UInt(5) // . => GrantAck
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val ReleaseAck = UInt(6) // .
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val GrantAck = UInt(0) // .
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def isA(x: UInt) = x <= Acquire
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def isB(x: UInt) = x <= Probe
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def isC(x: UInt) = x <= ReleaseData
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def isD(x: UInt) = x <= ReleaseAck
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}
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/**
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* The three primary TileLink permissions are:
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* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
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* (B)ranch: the agent is on an outwards path to
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* (N)one:
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* These permissions are permuted by transfer operations in various ways.
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* Operations can cap permissions, request for them to be grown or shrunk,
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* or for a report on their current status.
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*/
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object TLPermissions
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{
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val aWidth = 2
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val bdWidth = 2
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val cWidth = 3
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// Cap types (Grant = new permissions, Probe = permisions <= target)
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val toT = UInt(0, bdWidth)
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val toB = UInt(1, bdWidth)
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val toN = UInt(2, bdWidth)
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def isCap(x: UInt) = x <= toN
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// Grow types (Acquire = permissions >= target)
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val NtoB = UInt(0, aWidth)
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val NtoT = UInt(1, aWidth)
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val BtoT = UInt(2, aWidth)
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def isGrow(x: UInt) = x <= BtoT
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// Shrink types (ProbeAck, Release)
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val TtoB = UInt(0, cWidth)
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val TtoN = UInt(1, cWidth)
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val BtoN = UInt(2, cWidth)
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def isShrink(x: UInt) = x <= BtoN
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// Report types (ProbeAck)
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val TtoT = UInt(3, cWidth)
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val BtoB = UInt(4, cWidth)
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val NtoN = UInt(5, cWidth)
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def isReport(x: UInt) = x <= NtoN
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}
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object TLAtomics
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{
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val width = 3
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// Arithmetic types
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val MIN = UInt(0, width)
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val MAX = UInt(1, width)
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val MINU = UInt(2, width)
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val MAXU = UInt(3, width)
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val ADD = UInt(4, width)
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def isArithmetic(x: UInt) = x <= ADD
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// Logical types
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val XOR = UInt(0, width)
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val OR = UInt(1, width)
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val AND = UInt(2, width)
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val SWAP = UInt(3, width)
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def isLogical(x: UInt) = x <= SWAP
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}
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object TLHints
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{
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val width = 1
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val PREFETCH_READ = UInt(0, width)
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val PREFETCH_WRITE = UInt(1, width)
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}
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sealed trait TLChannel extends TLBundleBase {
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val channelName: String
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}
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sealed trait TLDataChannel extends TLChannel
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sealed trait TLAddrChannel extends TLDataChannel
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final class TLBundleA(params: TLBundleParameters)
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extends TLBundleBase(params) with TLAddrChannel
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{
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val channelName = "'A' channel"
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// fixed fields during multibeat:
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val opcode = UInt(width = 3)
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val param = UInt(width = List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max) // amo_opcode || grow perms || hint
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // from
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val address = UInt(width = params.addressBits) // to
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// variable fields during multibeat:
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val mask = UInt(width = params.dataBits/8)
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val data = UInt(width = params.dataBits)
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}
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final class TLBundleB(params: TLBundleParameters)
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extends TLBundleBase(params) with TLAddrChannel
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{
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val channelName = "'B' channel"
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// fixed fields during multibeat:
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val opcode = UInt(width = 3)
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val param = UInt(width = TLPermissions.bdWidth) // cap perms
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // to
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val address = UInt(width = params.addressBits) // from
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// variable fields during multibeat:
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val mask = UInt(width = params.dataBits/8)
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val data = UInt(width = params.dataBits)
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}
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final class TLBundleC(params: TLBundleParameters)
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extends TLBundleBase(params) with TLAddrChannel
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{
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val channelName = "'C' channel"
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// fixed fields during multibeat:
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val opcode = UInt(width = 3)
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val param = UInt(width = TLPermissions.cWidth) // shrink or report perms
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // from
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val address = UInt(width = params.addressBits) // to
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// variable fields during multibeat:
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val data = UInt(width = params.dataBits)
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val error = Bool() // AccessAck[Data]
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}
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final class TLBundleD(params: TLBundleParameters)
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extends TLBundleBase(params) with TLDataChannel
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{
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val channelName = "'D' channel"
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// fixed fields during multibeat:
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val opcode = UInt(width = 3)
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val param = UInt(width = TLPermissions.bdWidth) // cap perms
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // to
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val sink = UInt(width = params.sinkBits) // from
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val addr_lo = UInt(width = params.addrLoBits) // instead of mask
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// variable fields during multibeat:
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val data = UInt(width = params.dataBits)
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val error = Bool() // AccessAck[Data], Grant[Data]
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}
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final class TLBundleE(params: TLBundleParameters)
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extends TLBundleBase(params) with TLChannel
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{
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val channelName = "'E' channel"
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val sink = UInt(width = params.sinkBits) // to
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}
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class TLBundle(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val a = Decoupled(new TLBundleA(params))
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val b = Decoupled(new TLBundleB(params)).flip
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val c = Decoupled(new TLBundleC(params))
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val d = Decoupled(new TLBundleD(params)).flip
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val e = Decoupled(new TLBundleE(params))
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}
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object TLBundle
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{
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def apply(params: TLBundleParameters) = new TLBundle(params)
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}
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final class DecoupledSnoop[+T <: Data](gen: T) extends Bundle
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{
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val ready = Bool()
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val valid = Bool()
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val bits = gen.asOutput
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def fire(dummy: Int = 0) = ready && valid
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override def cloneType: this.type = new DecoupledSnoop(gen).asInstanceOf[this.type]
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}
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object DecoupledSnoop
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{
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def apply[T <: Data](i: DecoupledIO[T]) = {
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val out = Wire(new DecoupledSnoop(i.bits))
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out.ready := i.ready
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out.valid := i.valid
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out.bits := i.bits
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out
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}
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}
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class TLBundleSnoop(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val a = new DecoupledSnoop(new TLBundleA(params))
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val b = new DecoupledSnoop(new TLBundleB(params))
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val c = new DecoupledSnoop(new TLBundleC(params))
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val d = new DecoupledSnoop(new TLBundleD(params))
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val e = new DecoupledSnoop(new TLBundleE(params))
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}
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object TLBundleSnoop
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{
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def apply(x: TLBundle) = {
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val out = Wire(new TLBundleSnoop(x.params))
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out.a <> DecoupledSnoop(x.a)
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out.b <> DecoupledSnoop(x.b)
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out.c <> DecoupledSnoop(x.c)
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out.d <> DecoupledSnoop(x.d)
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out.e <> DecoupledSnoop(x.e)
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out
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}
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}
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class TLAsyncBundleBase(params: TLAsyncBundleParameters) extends GenericParameterizedBundle(params)
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class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
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{
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val a = new AsyncBundle(params.depth, new TLBundleA(params.base))
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val b = new AsyncBundle(params.depth, new TLBundleB(params.base)).flip
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val c = new AsyncBundle(params.depth, new TLBundleC(params.base))
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val d = new AsyncBundle(params.depth, new TLBundleD(params.base)).flip
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val e = new AsyncBundle(params.depth, new TLBundleE(params.base))
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}
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class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val a = RationalIO(new TLBundleA(params))
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val b = RationalIO(new TLBundleB(params)).flip
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val c = RationalIO(new TLBundleC(params))
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val d = RationalIO(new TLBundleD(params)).flip
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val e = RationalIO(new TLBundleE(params))
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}
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