261 lines
9.0 KiB
Scala
261 lines
9.0 KiB
Scala
package rocket
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import Chisel._;
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import Node._;
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import Constants._;
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import scala.math._;
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class ioDpathBTB extends Bundle()
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{
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val current_pc = UFix(VADDR_BITS, INPUT);
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val hit = Bool(OUTPUT);
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val target = UFix(VADDR_BITS, OUTPUT);
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val wen = Bool(INPUT);
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val clr = Bool(INPUT);
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val invalidate = Bool(INPUT);
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val correct_pc = UFix(VADDR_BITS, INPUT);
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val correct_target = UFix(VADDR_BITS, INPUT);
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}
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// fully-associative branch target buffer
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class rocketDpathBTB(entries: Int) extends Component
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{
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val io = new ioDpathBTB();
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val repl_way = LFSR16(io.wen)(log2up(entries)-1,0) // TODO: pseudo-LRU
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var hit_reduction = Bool(false)
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val hit = Wire() { Bool() }
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val update = Wire() { Bool() }
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var update_reduction = Bool(false)
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val mux = (new Mux1H(entries)) { Bits(width = VADDR_BITS) }
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for (i <- 0 until entries) {
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val tag = Reg() { UFix() }
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val target = Reg() { UFix() }
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val valid = Reg(resetVal = Bool(false))
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val my_hit = valid && tag === io.current_pc
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val my_update = valid && tag === io.correct_pc
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val my_clr = io.clr && my_update || io.invalidate
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val my_wen = io.wen && (my_update || !update && UFix(i) === repl_way)
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valid := !my_clr && (valid || my_wen)
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when (my_wen) {
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tag := io.correct_pc
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target := io.correct_target
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}
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hit_reduction = hit_reduction || my_hit
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update_reduction = update_reduction || my_update
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mux.io.sel(i) := my_hit
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mux.io.in(i) := target
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}
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hit := hit_reduction
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update := update_reduction
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io.hit := hit
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io.target := mux.io.out.toUFix
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}
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class ioDpathPCR extends Bundle()
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{
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val host = new ioHTIF()
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val r = new ioReadPort();
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val w = new ioWritePort();
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val status = Bits(32, OUTPUT);
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val ptbr = UFix(PADDR_BITS, OUTPUT);
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val evec = UFix(VADDR_BITS, OUTPUT);
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val exception = Bool(INPUT);
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val cause = UFix(6, INPUT);
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val badvaddr_wen = Bool(INPUT);
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val vec_irq_aux = Bits(64, INPUT)
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val vec_irq_aux_wen = Bool(INPUT)
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val pc = UFix(VADDR_BITS+1, INPUT);
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val eret = Bool(INPUT);
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val ei = Bool(INPUT);
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val di = Bool(INPUT);
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val ptbr_wen = Bool(OUTPUT);
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val irq_timer = Bool(OUTPUT);
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val irq_ipi = Bool(OUTPUT);
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val vecbank = Bits(8, OUTPUT)
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val vecbankcnt = UFix(4, OUTPUT)
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val vec_appvl = UFix(12, INPUT)
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val vec_nxregs = UFix(6, INPUT)
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val vec_nfregs = UFix(6, INPUT)
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}
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class rocketDpathPCR extends Component
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{
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val io = new ioDpathPCR();
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val reg_epc = Reg() { UFix() };
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val reg_badvaddr = Reg() { UFix() };
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val reg_ebase = Reg() { UFix() };
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val reg_count = Reg() { UFix() };
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val reg_compare = Reg() { UFix() };
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val reg_cause = Reg() { Bits() };
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val reg_tohost = Reg(resetVal = Bits(0, 64));
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val reg_fromhost = Reg(resetVal = Bits(0, 64));
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val reg_coreid = Reg() { Bits() }
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val reg_k0 = Reg() { Bits() };
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val reg_k1 = Reg() { Bits() };
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val reg_ptbr = Reg() { UFix() };
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val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
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val reg_error_mode = Reg(resetVal = Bool(false));
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val reg_status_vm = Reg(resetVal = Bool(false));
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val reg_status_im = Reg(resetVal = Bits(0,SR_IM_WIDTH));
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val reg_status_sx = Reg(resetVal = Bool(true));
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val reg_status_ux = Reg(resetVal = Bool(true));
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val reg_status_ec = Reg(resetVal = Bool(false));
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val reg_status_ef = Reg(resetVal = Bool(false));
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val reg_status_ev = Reg(resetVal = Bool(false));
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val reg_status_s = Reg(resetVal = Bool(true));
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val reg_status_ps = Reg(resetVal = Bool(false));
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val reg_status_et = Reg(resetVal = Bool(false));
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val r_irq_timer = Reg(resetVal = Bool(false));
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val r_irq_ipi = Reg(resetVal = Bool(true))
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val rdata = Wire() { Bits() };
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val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr)
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io.host.pcr_rep.valid := io.host.pcr_req.valid && !io.r.en && !io.host.pcr_req.bits.rw
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io.host.pcr_rep.bits := rdata
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val wen = io.w.en || io.host.pcr_req.valid && io.host.pcr_req.bits.rw
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val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_req.bits.addr)
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val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data)
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io.host.pcr_req.ready := Mux(io.host.pcr_req.bits.rw, !io.w.en, !io.r.en)
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io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR);
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io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
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io.evec := Mux(io.exception, reg_ebase, reg_epc)
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io.ptbr := reg_ptbr;
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io.host.debug.error_mode := reg_error_mode;
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io.r.data := rdata;
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io.vecbank := reg_vecbank
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var cnt = UFix(0,4)
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for (i <- 0 until 8)
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cnt = cnt + reg_vecbank(i)
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io.vecbankcnt := cnt(3,0)
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val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
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when (io.badvaddr_wen) {
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reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
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}
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when (io.vec_irq_aux_wen) {
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reg_badvaddr := io.vec_irq_aux.toUFix
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}
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when (io.exception) {
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when (!reg_status_et) {
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reg_error_mode := Bool(true)
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}
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.otherwise {
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reg_status_s := Bool(true);
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reg_status_ps := reg_status_s;
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reg_status_et := Bool(false);
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reg_epc := io.pc;
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reg_cause := io.cause;
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}
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}
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when (io.eret) {
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reg_status_s := reg_status_ps;
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reg_status_et := Bool(true);
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}
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when (reg_count === reg_compare) {
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r_irq_timer := Bool(true);
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}
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reg_count := reg_count + UFix(1);
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io.irq_timer := r_irq_timer;
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io.irq_ipi := r_irq_ipi;
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io.host.ipi.valid := Bool(false)
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io.host.ipi.bits := wdata
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when (wen) {
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when (waddr === PCR_STATUS) {
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reg_status_vm := wdata(SR_VM).toBool;
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reg_status_im := wdata(SR_IM_WIDTH+SR_IM,SR_IM);
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reg_status_sx := wdata(SR_S64).toBool;
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reg_status_ux := wdata(SR_U64).toBool;
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reg_status_s := wdata(SR_S).toBool;
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reg_status_ps := wdata(SR_PS).toBool;
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reg_status_ev := Bool(HAVE_VEC) && wdata(SR_EV).toBool;
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reg_status_ef := Bool(HAVE_FPU) && wdata(SR_EF).toBool;
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reg_status_ec := Bool(HAVE_RVC) && wdata(SR_EC).toBool;
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reg_status_et := wdata(SR_ET).toBool;
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}
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when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toUFix; }
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when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
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when (waddr === PCR_COUNT) { reg_count := wdata(31,0).toUFix; }
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when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
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when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) }
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when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
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when (waddr === PCR_TOHOST) { reg_tohost := wdata; reg_fromhost := Bits(0) }
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when (waddr === PCR_SEND_IPI) { io.host.ipi.valid := Bool(true) }
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when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
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when (waddr === PCR_K0) { reg_k0 := wdata; }
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when (waddr === PCR_K1) { reg_k1 := wdata; }
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when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) }
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}
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rdata := io.status // raddr === PCR_STATUS
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switch (raddr) {
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is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }
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is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); }
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is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
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is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); }
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is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); }
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is (PCR_CAUSE) { rdata := Cat(reg_cause(5), Bits(0,58), reg_cause(4,0)); }
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is (PCR_COREID) { rdata := reg_coreid }
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is (PCR_IMPL) { rdata := Bits(2) }
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is (PCR_FROMHOST) { rdata := reg_fromhost; }
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is (PCR_TOHOST) { rdata := reg_tohost; }
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is (PCR_K0) { rdata := reg_k0; }
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is (PCR_K1) { rdata := reg_k1; }
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is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
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is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
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is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
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}
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}
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class ioReadPort extends Bundle()
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{
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val addr = UFix(5, INPUT);
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val en = Bool(INPUT);
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val data = Bits(64, OUTPUT);
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}
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class ioWritePort extends Bundle()
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{
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val addr = UFix(5, INPUT);
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val en = Bool(INPUT);
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val data = Bits(64, INPUT);
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}
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class ioRegfile extends Bundle()
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{
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val r0 = new ioReadPort();
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val r1 = new ioReadPort();
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val w0 = new ioWritePort();
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}
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class rocketDpathRegfile extends Component
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{
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override val io = new ioRegfile();
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val regfile = Mem(32){ Bits(width=64) }
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regfile.setReadLatency(0);
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regfile.setTarget('inst);
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regfile.write(io.w0.addr, io.w0.data, io.w0.en);
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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}
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