78 lines
2.8 KiB
Scala
78 lines
2.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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// TODO: applies to all caches, for now
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case object CacheBlockBytes extends Field[Int](64)
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/** L2 Broadcast Hub configuration */
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case class BroadcastParams(
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nTrackers: Int = 4,
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bufferless: Boolean = false)
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case object BroadcastKey extends Field(BroadcastParams())
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/** L2 memory subsystem configuration */
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case class BankedL2Params(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: (Parameters, HasMemoryBus) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
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implicit val p = q
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val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusKey)
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val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
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val bh = LazyModule(new TLBroadcast(blockBytes, nTrackers, bufferless))
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(bh.node, bh.node)
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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case object BankedL2Key extends Field(BankedL2Params())
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/** Parameterization of the memory-side bus created for each memory channel */
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case class MemoryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.none,
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slaveBuffering: BufferParams = BufferParams.none
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) extends TLBusParams
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case object MemoryBusKey extends Field[MemoryBusParams]
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/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
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class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
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def fromCoherenceManager: TLInwardNode = inwardBufNode
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def toDRAMController: TLOutwardNode = outwardBufNode
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def toVariableWidthSlave: TLOutwardNode = outwardFragNode
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}
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trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBus {
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private val mbusParams = p(MemoryBusKey)
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private val MemoryBusParams(beatBytes, blockBytes, _, _) = mbusParams
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private val l2Params = p(BankedL2Key)
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val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params
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val nBanks = l2Params.nBanks
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val cacheBlockBytes = blockBytes
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require (isPow2(nMemoryChannels) || nMemoryChannels == 0)
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require (isPow2(nBanksPerChannel))
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require (isPow2(blockBytes))
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private val (in, out) = coherenceManager(p, this)
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private val mask = ~BigInt((nBanks-1) * blockBytes)
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val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
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val mbus = new MemoryBus(mbusParams)
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for (bank <- 0 until nBanksPerChannel) {
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val offset = (bank * nMemoryChannels) + channel
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ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
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mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * blockBytes, mask)))(out)
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}
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mbus
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}
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}
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