279 lines
10 KiB
Scala
279 lines
10 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
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val outerDataBeats = params(TLDataBeats)
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val outerDataBits = params(TLDataBits)
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val refillCyclesPerBeat = outerDataBits/rowBits
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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}
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abstract trait FrontendParameters extends L1CacheParameters
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abstract class FrontendBundle extends Bundle with FrontendParameters
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abstract class FrontendModule extends Module with FrontendParameters
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class FrontendReq extends CoreBundle {
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val pc = UInt(width = vaddrBitsExtended)
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}
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class FrontendResp extends CoreBundle {
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
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val mask = Bits(width = coreFetchWidth)
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val xcpt_if = Bool()
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}
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class CPUFrontendIO extends CoreBundle {
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val req = Valid(new FrontendReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_resp = Valid(new BTBResp).flip
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val invalidate = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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}
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class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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{
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val io = new Bundle {
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val cpu = new CPUFrontendIO().flip
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val ptw = new TLBPTWIO()
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val mem = new ClientUncachedTileLinkIO
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}
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val btb = Module(new BTB(btb_updates_out_of_order))
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val icache = Module(new ICache)
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val tlb = Module(new TLB)
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val s1_pc_ = Reg(UInt())
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val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
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val s1_same_block = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=UInt(START_ADDR))
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(btb.io.resp.bits)
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val s2_xcpt_if = Reg(init=Bool(false))
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val msb = vaddrBits-1
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val lsb = log2Up(coreFetchWidth*coreInstBytes)
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
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val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
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val icmiss = s2_valid && !icache.io.resp.valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
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val stall = io.cpu.resp.valid && !io.cpu.resp.ready
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when (!stall) {
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s1_same_block := s0_same_block && !tlb.io.resp.miss
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s1_pc_ := npc
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s2_valid := !icmiss
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when (!icmiss) {
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s2_pc := s1_pc
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s2_btb_resp_valid := btb.io.resp.valid
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when (btb.io.resp.valid) { s2_btb_resp_bits := btb.io.resp.bits }
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s2_xcpt_if := tlb.io.resp.xcpt_if
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}
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}
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when (io.cpu.req.valid) {
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s1_same_block := Bool(false)
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s1_pc_ := io.cpu.req.bits.pc
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s2_valid := Bool(false)
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}
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btb.io.req.valid := !stall && !icmiss
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
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io.ptw <> tlb.io.ptw
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tlb.io.req.valid := !stall && !icmiss
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tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
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tlb.io.req.bits.asid := UInt(0)
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(true)
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tlb.io.req.bits.store := Bool(false)
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io.mem <> icache.io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.idx := io.cpu.npc
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icache.io.invalidate := io.cpu.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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require(coreFetchWidth * coreInstBytes <= rowBytes)
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val fetch_data =
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if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
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else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
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for (i <- 0 until coreFetchWidth) {
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io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
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}
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val all_ones = UInt((1 << (coreFetchWidth+1))-1)
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val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
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io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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io.cpu.btb_resp.valid := s2_btb_resp_valid
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io.cpu.btb_resp.bits := s2_btb_resp_bits
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}
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class ICacheReq extends FrontendBundle {
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val idx = UInt(width = pgIdxBits)
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val ppn = UInt(width = ppnBits) // delayed one cycle
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val kill = Bool() // delayed one cycle
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}
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class ICacheResp extends FrontendBundle {
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val data = Bits(width = coreInstBits)
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val datablock = Bits(width = rowBits)
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}
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class ICache extends FrontendModule
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{
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val io = new Bundle {
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val req = Valid(new ICacheReq).flip
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val resp = Decoupled(new ICacheResp)
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val invalidate = Bool(INPUT)
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val mem = new ClientUncachedTileLinkIO
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}
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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require(pgIdxBits >= untagBits)
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val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val invalidated = Reg(Bool())
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val stall = !io.resp.ready
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val rdy = Wire(Bool())
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val s2_valid = Reg(init=Bool(false))
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val s2_addr = Reg(UInt(width = paddrBits))
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val s2_any_tag_hit = Wire(Bool())
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val s1_valid = Reg(init=Bool(false))
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val s1_pgoff = Reg(UInt(width = pgIdxBits))
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val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt
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val s1_tag = s1_addr(tagBits+untagBits-1,untagBits)
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val s0_valid = io.req.valid || s1_valid && stall
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val s0_pgoff = Mux(s1_valid && stall, s1_pgoff, io.req.bits.idx)
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s1_valid := io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
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when (io.req.valid && rdy) {
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s1_pgoff := io.req.bits.idx
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}
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s2_valid := s1_valid && rdy && !io.req.bits.kill || io.resp.valid && stall
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when (s1_valid && rdy && !stall) {
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s2_addr := s1_addr
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}
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val s2_tag = s2_addr(tagBits+untagBits-1,untagBits)
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val s2_idx = s2_addr(untagBits-1,blockOffBits)
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val s2_offset = s2_addr(blockOffBits-1,0)
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val s2_hit = s2_valid && s2_any_tag_hit
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val s2_miss = s2_valid && !s2_any_tag_hit
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rdy := state === s_ready && !s2_miss
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val narrow_grant = FlowThroughSerializer(io.mem.grant, refillCyclesPerBeat)
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val (refill_cnt, refill_wrap) = Counter(narrow_grant.fire(), refillCycles) //TODO Zero width wire
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val refill_done = state === s_refill && refill_wrap
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narrow_grant.ready := Bool(true)
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val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
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val entagbits = code.width(tagBits)
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val tag_array = SeqMem(Bits(width = entagbits*nWays), nSets)
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val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
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when (refill_done) {
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val wmask = FillInterleaved(entagbits, if (isDM) Bits(1) else UIntToOH(repl_way))
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val tag = code.encode(s2_tag).toUInt
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tag_array.write(s2_idx, Fill(nWays, tag), wmask)
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true))
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}
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when (io.invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s2_disparity = Wire(Vec(Bool(), nWays))
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for (i <- 0 until nWays)
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when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s2_idx), Bool(false)) }
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val s1_tag_match = Wire(Vec(Bool(), nWays))
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val s2_tag_hit = Wire(Vec(Bool(), nWays))
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val s2_dout = Reg(Vec(Bits(width = code.width(rowBits)), nWays))
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for (i <- 0 until nWays) {
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
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val s2_vb = Reg(Bool())
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val s2_tag_disparity = Reg(Bool())
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val s2_tag_match = Reg(Bool())
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val tag_out = tag_rdata(entagbits*(i+1)-1, entagbits*i)
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when (s1_valid && rdy && !stall) {
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s2_vb := s1_vb
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s2_tag_disparity := code.decode(tag_out).error
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s2_tag_match := s1_tag_match(i)
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}
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s1_tag_match(i) := tag_out(tagBits-1,0) === s1_tag
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s2_tag_hit(i) := s2_vb && s2_tag_match
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s2_disparity(i) := s2_vb && (s2_tag_disparity || code.decode(s2_dout(i)).error)
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}
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s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
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for (i <- 0 until nWays) {
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val data_array = SeqMem(Bits(width = code.width(rowBits)), nSets*refillCycles)
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val wen = narrow_grant.valid && repl_way === UInt(i)
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when (wen) {
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val e_d = code.encode(narrow_grant.bits.data).toUInt
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if(refillCycles > 1) data_array.write(Cat(s2_idx, refill_cnt), e_d)
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else data_array.write(s2_idx, e_d)
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}
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val s0_raddr = s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
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val s1_rdata = data_array.read(s0_raddr, !wen && s0_valid)
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// if s1_tag_match is critical, replace with partial tag check
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when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s2_dout(i) := s1_rdata }
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}
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val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits)))(coreInstBits-1,0))
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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// output signals
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io.resp.valid := s2_hit
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io.mem.acquire.valid := (state === s_request)
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io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> blockOffBits)
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// control state machine
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switch (state) {
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is (s_ready) {
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when (s2_miss) { state := s_request }
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invalidated := Bool(false)
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}
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is (s_request) {
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when (io.mem.acquire.ready) { state := s_refill_wait }
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}
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is (s_refill_wait) {
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when (io.mem.grant.valid) { state := s_refill }
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}
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is (s_refill) {
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when (refill_done) { state := s_ready }
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}
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}
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}
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