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riscv
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rocket-chip
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16d0f522b0
rocket-chip
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src
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main
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scala
History
Henry Cook
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
..
coreplex
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
diplomacy
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
groundtest
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
junctions
rocketchip: remove GlobalAddrMap completely
2016-11-21 21:13:26 -08:00
regmapper
regmapper RegisterCrossing: safe AsyncQueues are overkill here
2016-10-14 18:28:31 -07:00
rocket
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
rocketchip
rocketchip: don't waste too many sources on the AXI master port
2016-11-22 21:48:41 -08:00
uncore
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
unittest
junctions: get unit tests running again
2016-11-18 17:38:46 -08:00
util
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
2016-11-22 20:39:38 -08:00