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riscv/rocket-chip
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1474ab438d185be4f6357309246a7209271da2b2
rocket-chip/src/main/scala/tile
T
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Andrew Waterman 986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits
This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
..
BaseTile.scala
For Rockets without VM, widen vaddrBits to paddrBits
2017-10-08 01:21:47 -07:00
Core.scala
Define fetchBytes in HasCoreParams, not Frontend
2017-10-03 17:34:18 -07:00
FPU.scala
FPU : simplify pipeline register generation in FMA
2017-10-05 15:18:19 -07:00
Interrupts.scala
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
L1Cache.scala
tile: remove PAddrBits in favor of SharedMemoryTLEdge
2017-09-08 13:53:36 -07:00
LazyRoCC.scala
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
RocketTile.scala
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00
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