69 lines
2.8 KiB
Scala
69 lines
2.8 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import uncore._
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class MemDessert extends Module {
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val io = new MemDesserIO(params(HTIFWidth))
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val x = Module(new MemDesser(params(HTIFWidth)))
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io.narrow <> x.io.narrow
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io.wide <> x.io.wide
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}
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object VLSIUtils {
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def doOuterMemorySystemSerdes(llc: MemPipeIO, mem: MemIO,
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backup: MemSerializedIO, en: Bool, w: Int) {
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val mem_serdes = Module(new MemSerdes(w))
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val wide = mem_serdes.io.wide
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llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
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mem.req_cmd.valid := llc.req_cmd.valid && !en
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mem.req_cmd.bits := llc.req_cmd.bits
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wide.req_cmd.valid := llc.req_cmd.valid && en
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wide.req_cmd.bits := llc.req_cmd.bits
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llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
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mem.req_data.valid := llc.req_data.valid && !en
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mem.req_data.bits := llc.req_data.bits
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wide.req_data.valid := llc.req_data.valid && en
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wide.req_data.bits := llc.req_data.bits
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llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
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llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
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mem.resp.ready := Bool(true)
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backup <> mem_serdes.io.narrow
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}
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def padOutHTIFWithDividedClock(htif: HTIFModuleIO, child: MemSerializedIO,
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parent: MemSerializedIO, host: HostIO,
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en: Bool, htifW: Int) {
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val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
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hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
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hio.io.set_divisor.bits := htif.scr.wdata
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htif.scr.rdata(63) := hio.io.divisor
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hio.io.out_fast.valid := htif.host.out.valid || child.req.valid
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hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits))
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htif.host.out.ready := hio.io.out_fast.ready
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child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
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host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
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host.out.bits := hio.io.out_slow.bits
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parent.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
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hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.req.ready)
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val mem_backup_resp_valid = en && parent.resp.valid
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hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid
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hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits)
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host.in.ready := hio.io.in_slow.ready
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child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
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child.resp.bits := hio.io.in_fast.bits
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htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
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htif.host.in.bits := hio.io.in_fast.bits
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hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready)
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host.clk := hio.io.clk_slow
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host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
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}
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}
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