57 lines
1.5 KiB
Scala
57 lines
1.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.unittest
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import Chisel._
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import chisel3.experimental.MultiIOModule
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import freechips.rocketchip.config._
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import freechips.rocketchip.util._
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trait UnitTestIO {
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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trait HasUnitTestIO {
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val io: UnitTestIO
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}
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trait UnitTestLegacyModule extends HasUnitTestIO {
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val io = new Bundle with UnitTestIO
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}
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trait UnitTestModule extends MultiIOModule with HasUnitTestIO {
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val io = IO(new Bundle with UnitTestIO)
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ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
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}
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abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule {
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val testName = this.getClass.getSimpleName
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when (io.start) { printf(s"Started UnitTest $testName\n") }
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val timed_out = SimpleTimer(timeout, io.start, io.finished)
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assert(!timed_out, s"UnitTest $testName timed out")
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}
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case object UnitTests extends Field[Parameters => Seq[UnitTest]]
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class UnitTestSuite(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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}
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val tests = p(UnitTests)(p)
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val s_idle :: s_start :: s_busy :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val tests_finished = Vec(tests.map(_.io.finished)).reduce(_&&_)
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tests.foreach { _.io.start := (state === s_start) }
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io.finished := (state === s_done)
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when (state === s_idle) { state := s_start }
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when (state === s_start) { state := s_busy }
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when (state === s_busy && tests_finished) { state := s_done }
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}
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