260 lines
11 KiB
Scala
260 lines
11 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import freechips.rocketchip.amba.axi4._
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import scala.math.{min, max}
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class TLtoAXI4IdMap(tl: TLClientPortParameters, axi4: AXI4MasterPortParameters) {
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private val axiDigits = String.valueOf(axi4.endId-1).length()
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private val tlDigits = String.valueOf(tl.endSourceId-1).length()
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private val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s"
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private val sorted = tl.clients.sortWith(TLToAXI4.sortByType)
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val mapping: Seq[TLToAXI4IdMapEntry] = (sorted zip axi4.masters) map { case (c, m) =>
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TLToAXI4IdMapEntry(m.id, c.sourceId, c.name, c.supportsProbe, c.requestFifo)
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}
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def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
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}
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case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) {
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def pretty(fmt: String) = fmt.format(
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axi4Id.start,
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axi4Id.end,
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tlId.start,
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tlId.end,
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s""""$name"""",
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if (isCache) " [CACHE]" else "",
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if (requestFifo) " [FIFO]" else "")
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}
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case class TLToAXI4Node(stripBits: Int = 0)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
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dFn = { p =>
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p.clients.foreach { c =>
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require (c.sourceId.start % (1 << stripBits) == 0 &&
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c.sourceId.end % (1 << stripBits) == 0,
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s"Cannot strip bits of aligned client ${c.name}: ${c.sourceId}")
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}
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val clients = p.clients.sortWith(TLToAXI4.sortByType _)
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val idSize = clients.map { c => if (c.requestFifo) 1 else (c.sourceId.size >> stripBits) }
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val idStart = idSize.scanLeft(0)(_+_).init
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val masters = ((idStart zip idSize) zip clients) map { case ((start, size), c) =>
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AXI4MasterParameters(
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name = c.name,
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id = IdRange(start, start+size),
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aligned = true,
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maxFlight = Some(if (c.requestFifo) c.sourceId.size else (1 << stripBits)),
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nodePath = c.nodePath)
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}
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AXI4MasterPortParameters(
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masters = masters,
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userBits = log2Ceil(p.endSourceId) + 4)
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},
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uFn = { p => TLManagerPortParameters(
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managers = p.slaves.map { case s =>
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TLManagerParameters(
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address = s.address,
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resources = s.resources,
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regionType = s.regionType,
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executable = s.executable,
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nodePath = s.nodePath,
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supportsGet = s.supportsRead,
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supportsPutFull = s.supportsWrite,
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supportsPutPartial = s.supportsWrite,
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fifoId = Some(0))},
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beatBytes = p.beatBytes,
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minLatency = p.minLatency)
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})
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class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0)(implicit p: Parameters) extends LazyModule
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{
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val node = TLToAXI4Node(stripBits)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val slaves = edgeOut.slave.slaves
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// All pairs of slaves must promise that they will never interleave data
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require (slaves(0).interleavedId.isDefined)
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slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
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// Construct the source=>ID mapping table
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val map = new TLtoAXI4IdMap(edgeIn.client, edgeOut.master)
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val sourceStall = Wire(Vec(edgeIn.client.endSourceId, Bool()))
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val sourceTable = Wire(Vec(edgeIn.client.endSourceId, out.aw.bits.id))
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val idStall = Wire(init = Vec.fill(edgeOut.master.endId) { Bool(false) })
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var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] }
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map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) =>
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for (i <- 0 until tlId.size) {
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val id = axi4Id.start + (if (fifo) 0 else (i >> stripBits))
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sourceStall(tlId.start + i) := idStall(id)
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sourceTable(tlId.start + i) := UInt(id)
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}
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if (fifo) { idCount(axi4Id.start) = Some(tlId.size) }
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}
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adapterName.foreach { n =>
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println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n")
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ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""")
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}
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// We need to keep the following state from A => D: (size, source)
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// All of those fields could potentially require 0 bits (argh. Chisel.)
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// We will pack all of that extra information into the user bits.
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val sourceBits = log2Ceil(edgeIn.client.endSourceId)
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val sizeBits = log2Ceil(edgeIn.maxLgSize+1)
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val stateBits = sizeBits + sourceBits // could be 0
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require (stateBits <= out.aw.bits.params.userBits)
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val a_address = edgeIn.address(in.a.bits)
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val a_source = in.a.bits.source
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val a_size = edgeIn.size(in.a.bits)
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val a_isPut = edgeIn.hasData(in.a.bits)
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val (a_first, a_last, _) = edgeIn.firstlast(in.a)
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// Make sure the fields are within the bounds we assumed
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assert (a_source < UInt(BigInt(1) << sourceBits))
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assert (a_size < UInt(BigInt(1) << sizeBits))
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// Carefully pack/unpack fields into the state we send
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val baseEnd = 0
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val (sourceEnd, sourceOff) = (sourceBits + baseEnd, baseEnd)
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val (sizeEnd, sizeOff) = (sizeBits + sourceEnd, sourceEnd)
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require (sizeEnd == stateBits)
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val a_state = (a_source << sourceOff) | (a_size << sizeOff)
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val r_state = out.r.bits.user.getOrElse(UInt(0))
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val r_source = if (sourceBits > 0) r_state(sourceEnd-1, sourceOff) else UInt(0)
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val r_size = if (sizeBits > 0) r_state(sizeEnd -1, sizeOff) else UInt(0)
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val b_state = out.b.bits.user.getOrElse(UInt(0))
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val b_source = if (sourceBits > 0) b_state(sourceEnd-1, sourceOff) else UInt(0)
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val b_size = if (sizeBits > 0) b_state(sizeEnd -1, sizeOff) else UInt(0)
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// We need these Queues because AXI4 queues are irrevocable
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val depth = if (combinational) 1 else 2
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val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
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val out_w = Wire(out.w)
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out.w <> Queue.irrevocable(out_w, entries=depth, flow=combinational)
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val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational)
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// Fan out the ARW channel to AR and AW
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out.ar.bits := queue_arw.bits
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out.aw.bits := queue_arw.bits
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out.ar.valid := queue_arw.valid && !queue_arw.bits.wen
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out.aw.valid := queue_arw.valid && queue_arw.bits.wen
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queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready)
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val beatBytes = edgeIn.manager.beatBytes
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val maxSize = UInt(log2Ceil(beatBytes))
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val doneAW = RegInit(Bool(false))
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when (in.a.fire()) { doneAW := !a_last }
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val arw = out_arw.bits
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arw.wen := a_isPut
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arw.id := sourceTable(a_source)
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arw.addr := a_address
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arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes)
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arw.size := Mux(a_size >= maxSize, maxSize, a_size)
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arw.burst := AXI4Parameters.BURST_INCR
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arw.lock := UInt(0) // not exclusive (LR/SC unsupported b/c no forward progress guarantee)
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arw.cache := UInt(0) // do not allow AXI to modify our transactions
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arw.prot := AXI4Parameters.PROT_PRIVILEDGED
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arw.qos := UInt(0) // no QoS
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arw.user.foreach { _ := a_state }
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val stall = sourceStall(in.a.bits.source) && a_first
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in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready)
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out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, Bool(true))
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out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready)
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out_w.bits.data := in.a.bits.data
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out_w.bits.strb := in.a.bits.mask
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out_w.bits.last := a_last
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// R and B => D arbitration
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val r_holds_d = RegInit(Bool(false))
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when (out.r.fire()) { r_holds_d := !out.r.bits.last }
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// Give R higher priority than B
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val r_wins = out.r.valid || r_holds_d
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out.r.ready := in.d.ready
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out.b.ready := in.d.ready && !r_wins
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in.d.valid := Mux(r_wins, out.r.valid, out.b.valid)
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val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
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val b_error = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
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val reg_error = RegInit(Bool(false))
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when (out.r.fire()) { reg_error := !out.r.bits.last && (reg_error || r_error) }
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val r_d = edgeIn.AccessAck(r_source, r_size, UInt(0), reg_error || r_error)
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val b_d = edgeIn.AccessAck(b_source, b_size, b_error)
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in.d.bits := Mux(r_wins, r_d, b_d)
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in.d.bits.data := out.r.bits.data // avoid a costly Mux
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// We need to track if any reads or writes are inflight for a given ID.
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// If the opposite type arrives, we must stall until it completes.
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val a_sel = UIntToOH(arw.id, edgeOut.master.endId).toBools
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val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).toBools
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val d_last = Mux(r_wins, out.r.bits.last, Bool(true))
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// If FIFO was requested, ensure that R+W ordering is preserved
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(a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) =>
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// AXI does not guarantee read vs. write ordering. In particular, if we
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// are in the middle of receiving a read burst and then issue a write,
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// the write might affect the read burst. This violates FIFO behaviour.
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// To solve this, we must wait until the last beat of a burst, but this
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// means that a TileLink master which performs early source reuse can
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// have one more transaction inflight than we promised AXI; stall it too.
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val maxCount = n.getOrElse(1)
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val count = RegInit(UInt(0, width = log2Ceil(maxCount + 1)))
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val write = Reg(Bool())
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val idle = count === UInt(0)
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val inc = as && out_arw.fire()
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val dec = ds && d_last && in.d.fire()
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count := count + inc.asUInt - dec.asUInt
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assert (!dec || count =/= UInt(0)) // underflow
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assert (!inc || count =/= UInt(maxCount)) // overflow
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when (inc) { write := arw.wen }
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// If only one transaction can be inflight, it can't mismatch
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val mismatch = if (maxCount > 1) { write =/= arw.wen } else { Bool(false) }
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s := (!idle && mismatch) || (count === UInt(maxCount))
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}
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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}
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object TLToAXI4
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{
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def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) =
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{
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val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits))
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tl2axi4.node
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}
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def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
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if ( a.supportsProbe && !b.supportsProbe) return false
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if (!a.supportsProbe && b.supportsProbe) return true
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if ( a.requestFifo && !b.requestFifo ) return false
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if (!a.requestFifo && b.requestFifo ) return true
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return false
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}
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}
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