110 lines
4.3 KiB
Scala
110 lines
4.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class SystemBusParams(
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beatBytes: Int,
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blockBytes: Int,
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pbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams
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case object SystemBusKey extends Field[SystemBusParams]
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "system_bus")
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with HasTLXbarPhy {
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private val master_splitter = LazyModule(new TLSplitter)
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inwardNode :=* master_splitter.node
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protected def fixFromThenSplit(policy: TLFIFOFixer.Policy, buffer: BufferParams): TLInwardNode =
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master_splitter.node :=* TLBuffer(buffer) :=* TLFIFOFixer(policy)
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def busView = master_splitter.node.edges.in.head
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def toPeripheryBus(gen: => TLNode): TLOutwardNode = {
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to("pbus") {
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(gen
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:= TLFIFOFixer(TLFIFOFixer.all)
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:= TLWidthWidget(params.beatBytes)
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:= bufferTo(params.pbusBuffer))
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}
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}
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def toMemoryBus(gen: => TLInwardNode) {
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to("mbus") { gen := delayNode := outwardNode }
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}
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def toSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= bufferTo(buffer) }
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}
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def toSplitSlave[D,U,E,B <: Data]
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(name: Option[String] = None)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :=* master_splitter.node }
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}
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def toFixedWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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}
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def toVariableWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fragmentTo(buffer) }
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}
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def fromFrontBus(gen: => TLNode): TLInwardNode = {
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from("front_bus") { master_splitter.node :=* gen }
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}
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def fromTile
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(name: Option[String], buffer: BufferParams = BufferParams.none, cork: Option[Boolean] = None)
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(gen: => TLNode): TLInwardNode = {
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from("tile" named name) {
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fixFromThenSplit(TLFIFOFixer.allUncacheable, buffer) :=* gen
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}
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}
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def toFixedWidthPort[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("port" named name) { gen := fixedWidthTo(buffer) }
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}
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def fromPort[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
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TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
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from("port" named name) { fixFromThenSplit(TLFIFOFixer.all, buffer) :=* gen }
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}
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def fromCoherentMaster[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
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TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
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from("coherent_master" named name) { fixFrom(TLFIFOFixer.all, buffer) :=* gen }
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}
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def fromMaster[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
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TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
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from("master" named name) { fixFromThenSplit(TLFIFOFixer.all, buffer) :=* gen }
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}
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}
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