270 lines
9.7 KiB
Scala
270 lines
9.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.util._
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/** Specifies the size and width of external memory ports */
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case class MasterPortParams(
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base: BigInt,
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size: BigInt,
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beatBytes: Int,
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idBits: Int,
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maxXferBytes: Int = 256,
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executable: Boolean = true)
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case object ExtMem extends Field[MasterPortParams]
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case object ExtBus extends Field[MasterPortParams]
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/** Specifies the width of external slave ports */
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case class SlavePortParams(beatBytes: Int, idBits: Int, sourceBits: Int)
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case object ExtIn extends Field[SlavePortParams]
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///// The following traits add ports to the sytem, in some cases converting to different interconnect standards
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/** Adds a port to the system intended to master an AXI4 DRAM controller. */
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trait HasMasterAXI4MemPort { this: BaseSubsystem =>
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val module: HasMasterAXI4MemPortModuleImp
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private val params = p(ExtMem)
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private val portName = "axi4"
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private val device = new MemoryDevice
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val nMemoryChannels: Int
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val mem_axi4 = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
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val base = AddressSet(params.base, params.size-1)
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val filter = AddressSet(channel * cacheBlockBytes, ~((nMemoryChannels-1) * cacheBlockBytes))
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AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = base.intersect(filter).toList,
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resources = device.reg,
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regionType = RegionType.UNCACHED, // cacheable
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executable = true,
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supportsWrite = TransferSizes(1, cacheBlockBytes),
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supportsRead = TransferSizes(1, cacheBlockBytes),
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interleavedId = Some(0))), // slave does not interleave read responses
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beatBytes = params.beatBytes)
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})
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memBuses.map { m =>
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mem_axi4 := m.toDRAMController(Some(portName)) {
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(AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
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}
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}
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}
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasMasterAXI4MemPortBundle {
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implicit val p: Parameters
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val mem_axi4: HeterogeneousBag[AXI4Bundle]
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val nMemoryChannels: Int
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def connectSimAXIMem(dummy: Int = 1) = {
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if (nMemoryChannels > 0) {
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val mem = LazyModule(new SimAXIMem(nMemoryChannels))
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Module(mem.module).io.axi4 <> mem_axi4
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}
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}
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}
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/** Actually generates the corresponding IO in the concrete Module */
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trait HasMasterAXI4MemPortModuleImp extends LazyModuleImp with HasMasterAXI4MemPortBundle {
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val outer: HasMasterAXI4MemPort
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val mem_axi4 = IO(HeterogeneousBag.fromNode(outer.mem_axi4.in))
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(mem_axi4 zip outer.mem_axi4.in) foreach { case (i, (o, _)) => i <> o }
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val nMemoryChannels = outer.nMemoryChannels
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}
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/** Adds a AXI4 port to the system intended to master an MMIO device bus */
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trait HasMasterAXI4MMIOPort { this: BaseSubsystem =>
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private val params = p(ExtBus)
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private val portName = "mmio_port_axi4"
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private val device = new SimpleBus(portName.kebab, Nil)
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val mmio_axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = AddressSet.misaligned(params.base, params.size),
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resources = device.ranges,
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executable = params.executable,
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supportsWrite = TransferSizes(1, params.maxXferBytes),
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supportsRead = TransferSizes(1, params.maxXferBytes))),
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beatBytes = params.beatBytes)))
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mmio_axi4 := sbus.toFixedWidthPort(Some(portName)) {
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(AXI4Buffer()
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:= AXI4UserYanker()
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:= AXI4Deinterleaver(sbus.blockBytes)
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:= AXI4IdIndexer(params.idBits)
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:= TLToAXI4())
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}
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}
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasMasterAXI4MMIOPortBundle {
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implicit val p: Parameters
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val mmio_axi4: HeterogeneousBag[AXI4Bundle]
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def connectSimAXIMMIO(dummy: Int = 1) {
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val mmio_mem = LazyModule(new SimAXIMem(1, 4096))
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Module(mmio_mem.module).io.axi4 <> mmio_axi4
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}
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}
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/** Actually generates the corresponding IO in the concrete Module */
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trait HasMasterAXI4MMIOPortModuleImp extends LazyModuleImp with HasMasterAXI4MMIOPortBundle {
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val outer: HasMasterAXI4MMIOPort
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val mmio_axi4 = IO(HeterogeneousBag.fromNode(outer.mmio_axi4.in))
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(mmio_axi4 zip outer.mmio_axi4.in) foreach { case (i, (o, _)) => i <> o }
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}
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/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */
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trait HasSlaveAXI4Port { this: BaseSubsystem =>
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private val params = p(ExtIn)
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private val portName = "slave_port_axi4"
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val l2FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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name = portName.kebab,
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id = IdRange(0, 1 << params.idBits))))))
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private val fifoBits = 1
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fbus.fromPort(Some(portName), buffer = BufferParams.default) {
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(TLWidthWidget(params.beatBytes)
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:= AXI4ToTL()
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:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
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:= AXI4Fragmenter()
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:= AXI4IdIndexer(fifoBits))
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} := l2FrontendAXI4Node
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}
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasSlaveAXI4PortBundle {
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implicit val p: Parameters
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val l2_frontend_bus_axi4: HeterogeneousBag[AXI4Bundle]
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def tieOffAXI4SlavePort(dummy: Int = 1) {
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l2_frontend_bus_axi4.foreach { l2_axi4 =>
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l2_axi4.ar.valid := Bool(false)
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l2_axi4.aw.valid := Bool(false)
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l2_axi4.w .valid := Bool(false)
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l2_axi4.r .ready := Bool(true)
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l2_axi4.b .ready := Bool(true)
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}
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}
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}
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/** Actually generates the corresponding IO in the concrete Module */
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trait HasSlaveAXI4PortModuleImp extends LazyModuleImp with HasSlaveAXI4PortBundle {
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val outer: HasSlaveAXI4Port
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val l2_frontend_bus_axi4 = IO(HeterogeneousBag.fromNode(outer.l2FrontendAXI4Node.out).flip)
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(outer.l2FrontendAXI4Node.out zip l2_frontend_bus_axi4) foreach { case ((i, _), o) => i <> o }
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}
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/** Adds a TileLink port to the system intended to master an MMIO device bus */
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trait HasMasterTLMMIOPort { this: BaseSubsystem =>
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private val params = p(ExtBus)
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private val portName = "mmio_port_tl"
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private val device = new SimpleBus(portName.kebab, Nil)
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val mmio_tl = TLManagerNode(Seq(TLManagerPortParameters(
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managers = Seq(TLManagerParameters(
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address = AddressSet.misaligned(params.base, params.size),
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resources = device.ranges,
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executable = params.executable,
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supportsGet = TransferSizes(1, sbus.blockBytes),
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supportsPutFull = TransferSizes(1, sbus.blockBytes),
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supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
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beatBytes = params.beatBytes)))
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mmio_tl := sbus.toFixedWidthPort(Some(portName)) {
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TLBuffer() := TLSourceShrinker(1 << params.idBits)
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}
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}
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasMasterTLMMIOPortBundle {
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implicit val p: Parameters
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val mmio_tl: HeterogeneousBag[TLBundle]
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def tieOffTLMMIO(dummy: Int = 1) {
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mmio_tl.foreach { tl =>
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tl.a.ready := Bool(true)
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tl.b.valid := Bool(false)
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tl.c.ready := Bool(true)
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tl.d.valid := Bool(false)
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tl.e.ready := Bool(true)
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}
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}
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}
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/** Actually generates the corresponding IO in the concrete Module */
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trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle {
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val outer: HasMasterTLMMIOPort
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val mmio_tl = IO(HeterogeneousBag.fromNode(outer.mmio_tl.in))
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(mmio_tl zip outer.mmio_tl.in) foreach { case (i, (o, _)) => i <> o }
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}
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/** Adds an TL port to the system intended to be a slave on an MMIO device bus.
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* NOTE: this port is NOT allowed to issue Acquires.
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*/
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trait HasSlaveTLPort { this: BaseSubsystem =>
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private val params = p(ExtIn)
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private val portName = "slave_port_tl"
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val l2FrontendTLNode = TLClientNode(Seq(TLClientPortParameters(
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clients = Seq(TLClientParameters(
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name = portName.kebab,
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sourceId = IdRange(0, 1 << params.idBits))))))
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sbus.fromPort(Some(portName)) {
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TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes)
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} := l2FrontendTLNode
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}
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasSlaveTLPortBundle {
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implicit val p: Parameters
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val l2_frontend_bus_tl: HeterogeneousBag[TLBundle]
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def tieOffSlaveTLPort(dummy: Int = 1) {
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l2_frontend_bus_tl.foreach { tl =>
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tl.a.valid := Bool(false)
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tl.b.ready := Bool(true)
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tl.c.valid := Bool(false)
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tl.d.ready := Bool(true)
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tl.e.valid := Bool(false)
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}
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}
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}
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/** Actually generates the corresponding IO in the concrete Module */
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trait HasSlaveTLPortModuleImp extends LazyModuleImp with HasSlaveTLPortBundle {
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val outer: HasSlaveTLPort
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val l2_frontend_bus_tl = IO(HeterogeneousBag.fromNode(outer.l2FrontendTLNode.out).flip)
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(outer.l2FrontendTLNode.in zip l2_frontend_bus_tl) foreach { case ((i, _), o) => i <> o }
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}
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/** Memory with AXI port for use in elaboratable test harnesses. */
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class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) extends LazyModule {
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val config = p(ExtMem)
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val totalSize = if (forceSize > 0) forceSize else config.size
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val size = totalSize / channels
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require(totalSize % channels == 0)
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val node = AXI4MasterNode(Seq.fill(channels) {
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AXI4MasterPortParameters(Seq(AXI4MasterParameters(
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name = "dut",
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id = IdRange(0, 1 << config.idBits)
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)))
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})
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for (i <- 0 until channels) {
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val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
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sram.node := AXI4Buffer() := AXI4Fragmenter() := node
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}
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val axi4 = HeterogeneousBag.fromNode(node.out).flip
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})
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(node.out zip io.axi4) foreach { case ((i, _), o) => i <> o }
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}
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}
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