77 lines
2.8 KiB
Scala
77 lines
2.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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// TODO: applies to all caches, for now
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case object CacheBlockBytes extends Field[Int](64)
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/** L2 Broadcast Hub configuration */
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case class BroadcastParams(
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nTrackers: Int = 4,
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bufferless: Boolean = false)
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case object BroadcastKey extends Field(BroadcastParams())
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/** L2 memory subsystem configuration */
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case class BankedL2Params(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: BaseSubsystem => (TLInwardNode, TLOutwardNode, () => Option[Bool]) = { subsystem =>
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implicit val p = subsystem.p
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val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
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val bh = LazyModule(new TLBroadcast(subsystem.memBusBlockBytes, nTrackers, bufferless))
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val ww = LazyModule(new TLWidthWidget(subsystem.sbus.beatBytes))
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ww.node :*= bh.node
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(bh.node, ww.node, () => None)
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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case object BankedL2Key extends Field(BankedL2Params())
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/** Parameterization of the memory-side bus created for each memory channel */
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case class MemoryBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams
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case object MemoryBusKey extends Field[MemoryBusParams]
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/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
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class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "memory_bus")(p)
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with HasTLXbarPhy {
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def fromCoherenceManager
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLInwardNode = {
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from("coherence_manager" named name) {
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inwardNode := TLBuffer(buffer) := gen
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}
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}
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def toDRAMController[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[ TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle, D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("memory_controller" named name) { gen := bufferTo(buffer) }
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}
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def toVariableWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fragmentTo(buffer) }
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}
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def toFixedWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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}
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}
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