47 lines
1.4 KiB
Scala
47 lines
1.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.regmapper._
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case class ExampleParams(num: Int, address: BigInt)
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trait ExampleBundle
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{
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val params: ExampleParams
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val gpio = UInt(width = params.num)
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}
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trait ExampleModule extends HasRegMap
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{
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val params: ExampleParams
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val io: ExampleBundle
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val interrupts: Vec[Bool]
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val state = RegInit(UInt(0, width = params.num))
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val pending = RegInit(UInt(0xf, width = 4))
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io.gpio := state
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interrupts := pending.toBools
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regmap(
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0 -> Seq(
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RegField(params.num, state,
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RegFieldDesc("state", "State: Example of a R/W Register with description.", reset = Some(0)))),
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4 -> Seq(
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RegField.w1ToClear(4, pending, state,
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Some(RegFieldDesc("pending", "Pending: Example of a special (W1ToC) Register. " +
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"Writing a bit here causes it to be reset to 0. " +
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"The bits are set when the corresponding bit in 'state' is high.",
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reset=Some(0xF), volatile=true))))
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)
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}
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// Create a concrete TL2 version of the abstract Example slave
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class TLExample(params: ExampleParams)(implicit p: Parameters)
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extends TLRegisterRouter(params.address, "somedev", Seq("ucbbar,random-interface"), 4)(
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new TLRegBundle(params, _) with ExampleBundle)(
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new TLRegModule(params, _, _) with ExampleModule)
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