100 lines
3.3 KiB
Scala
100 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import scala.math.{min,max}
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object CLINTConsts
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{
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def msipOffset(hart: Int) = hart * msipBytes
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def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
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def timeOffset = 0xbff8
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def msipBytes = 4
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def timecmpBytes = 8
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def size = 0x10000
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def timeWidth = 64
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def ipiWidth = 32
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def ints = 2
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}
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case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
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{
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def address = AddressSet(baseAddress, CLINTConsts.size-1)
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}
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case object CLINTKey extends Field(CLINTParams())
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class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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import CLINTConsts._
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// clint0 => at most 4095 devices
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val device = new SimpleDevice("clint", Seq("riscv,clint0")) {
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override val alwaysExtended = true
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}
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val node = TLRegisterNode(
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address = Seq(params.address),
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device = device,
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beatBytes = beatBytes)
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val intnode = IntNexusNode(
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
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outputRequiresInput = false)
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lazy val module = new LazyModuleImp(this) {
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require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
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val io = IO(new Bundle {
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val rtcTick = Bool(INPUT)
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})
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val time = RegInit(UInt(0, width = timeWidth))
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when (io.rtcTick) { time := time + UInt(1) }
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val nTiles = intnode.out.size
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val timecmp = Seq.fill(nTiles) { Reg(UInt(width = timeWidth)) }
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val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
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val (intnode_out, _) = intnode.out.unzip
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intnode_out.zipWithIndex.foreach { case (int, i) =>
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int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
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int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
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}
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/* 0000 msip hart 0
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* 0004 msip hart 1
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* 4000 mtimecmp hart 0 lo
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* 4004 mtimecmp hart 0 hi
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* 4008 mtimecmp hart 1 lo
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* 400c mtimecmp hart 1 hi
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* bff8 mtime lo
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* bffc mtime hi
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*/
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node.regmap(
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0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) =>
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RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
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timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
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RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
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timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),
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RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
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)
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}
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}
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/** Trait that will connect a CLINT to a subsystem */
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trait HasPeripheryCLINT { this: BaseSubsystem =>
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val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("clint")) { clint.node }
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}
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